A Low-Power 22-bit Incremental ADC

A comparative design study of continuous‐time incremental sigma‐delta ADC architectures

“…All the existing CT IΣ∆ ADCs and some representative DT IΣ∆ ADCs have been included in this comparison. Note that only in [3] included. As shown in Figure 20, the three implemented CT IΣ∆ ADCs improve noticeably the FOMs of existing CT IΣ∆ ADCs.…”

“…During the last decade, different approaches have been proposed to significantly enhance the conversion speed and/or resolution of IΣ∆ ADCs. The most popular alternatives are high-order architectures [3,4,19]. Other popular alternatives are the extended counting (EC) [5,6] and the extended range (ER) [2] architectures, which combine the IΣ∆ ADC with a low-power Nyquist-rate ADC.…”

Design considerations for pipelined continuous-time incremental Sigma-Delta ADCs

“…Compared to a conventional pipeline ADC stage, a CT IΣ∆ ADC stage has several advantages. By employing noise shaping and CT−IΣ∆ (1,2) CT−IΣ∆ (1,3) CT−IΣ∆ (2,2) CT−IΣ∆ (2,3) CT−IΣ∆ (3,1) CT−IΣ∆ (3,2) oversampling, it achieves higher resolution with a 1-bit ADC, and hence avoids the need to implement a flash ADC and a multi-level DAC. Also, it does not require a subtractor for residue generation and a gain block for matching the input range of the subsequent stage.…”

“…The restricted batterylife and chip area in biosensors impose challenges in designing power-efficient IΣ∆ ADCs that meet both the bandwidth and resolution specifications. High-order [2] and extended-range (ER) [3] IΣ∆ ADCs using discrete-time (DT) implementation have been proposed to reduce the number of cycles per conversion, leading to better power-efficiency than the firstorder IΣ∆ ADC. A high-order continuous-time (CT) IΣ∆ ADC [4] has been developed lately, aiming to take advantage of the relaxed settling and bandwidth requirements of active blocks in CT loop filters.…”

Calibration Techniques for the Elimination of Non-Monotonic Errors and the Linearity Improvement of A/D Converters

“…1a where each resistor R has been replaced with a resistor R-kΔR connected in series with 2k trimming ΔR resistors that can be bypassed by the calibration algorithm or at a final stage of the fabrication process. High precision capacitors are used in several ADC architectures that are based on charge redistribution, integrators, Sigma-Delta ADCs etc (Quiquempoix et al, 2006). Capacitor trimming can be performed in a similar way to the resistors whenever high precision capacitors have to be used (Wit et al, 1993).…”