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The ALICE1 chip is a mixed-mode integrated circuit to read out silicon pixel detectors used for particle tracking in the ALICE Silicon Pixel Detector or particle identification in the LHCb Ring Imaging Cherenkov detector. The chip will be fabricated in a commercial 0.252m technology and transistors are designed with a radiation-tolerant geometry. It consists of 256 K 32 pixel cells, each of 502m K 4002m, and can be operated in one of two modes. In tracking mode, all cells are read out. In particle identification mode, 8 cells are grouped together, reducing the effective granularity to 32 K 32 cells of 4002m K 4002m. The cell architecture is described in detail, together with the two operational modes and issues of system integration.

In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (∆Σ) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed. Since line-frequency noise suppression is often important in measurement applications, modulators followed by sinc k filters are also analyzed. Equations are derived for the estimation of the required number of cycles for a given resolution and architecture. Finally, the design and implementation of a third-order incremental converter with a fourth-order sinc filter is briefly discussed.

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