IEEE Custom Integrated Circuits Conference 2006 2006
DOI: 10.1109/cicc.2006.320960
|View full text |Cite
|
Sign up to set email alerts
|

Incremental Delta-Sigma Structures for DC Measurement: an Overview

Abstract: In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (∆Σ) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed. Since line-frequency noise suppression is often important in measurement applications, modulators followed by sinc k filters are also analyzed. Equations are deriv… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
14
0

Year Published

2008
2008
2024
2024

Publication Types

Select...
6
1
1

Relationship

0
8

Authors

Journals

citations
Cited by 27 publications
(14 citation statements)
references
References 14 publications
(32 reference statements)
0
14
0
Order By: Relevance
“…Since the counter outputs a code for every radian change in its input, the counter gain is equal to (code/radian). The digital differentiation can be approximated with the transfer function of continuous time differentiation as follows: (12) where is the clock period. For frequencies much smaller than the clock frequency,…”
Section: A Gain Of a Vco Adc With Counter Based Fdcmentioning
confidence: 99%
See 1 more Smart Citation
“…Since the counter outputs a code for every radian change in its input, the counter gain is equal to (code/radian). The digital differentiation can be approximated with the transfer function of continuous time differentiation as follows: (12) where is the clock period. For frequencies much smaller than the clock frequency,…”
Section: A Gain Of a Vco Adc With Counter Based Fdcmentioning
confidence: 99%
“…Incremental data converter (IDC) [12] is another architecture suitable for low-bandwidth high resolution applications. An IDC is essentially a discrete time delta-sigma ADC that is reset periodically to perform sample-by-sample conversion.…”
mentioning
confidence: 99%
“…I NCREMENTAL analog-to-digital converter (IDC), also known as charge-balancing delta-sigma () converter, has been widely used for low-bandwidth signal conversions since it was introduced in [1]. It enjoys the nature of achieving high resolution without precise analog elements matching and can be easily multiplexed between multiple input channels [2]. IDCs are particularly popular in instrumentation applications that require high conversion precision, such as high linearity, low offset, and precise gain [3].…”
Section: Introductionmentioning
confidence: 99%
“…has been used not only for ER [2] but also for several incremental implementations [5], [7]- [10], where H NC (z) has been obtained by setting an upper limit of the ADC I quantization error based on the bounded output of the last integrator [11]. The performance improvement of ER implementations with respect to such IΣΔ ADCs can be verified by calculating the SQNR of the ADC I and relating it to (20).…”
Section: E E E P R O O Fmentioning
confidence: 99%
“…, and (31) reduces to (11). Under mismatches, however, there will be a "leak" of V (z, m) into the ADC ERI quantization error which will be given by…”
Section: Eriσδ Adc Nonideal Behaviormentioning
confidence: 99%