A low-power 6.6-Gb/s wireline transceiver for low-cost FPGAs in 28nm CMOS

Savoj, Jafar; Hsieh, Kenny; An, Fu-Tai; Buckley, Michael; Im, Jungho; Jiang, Xuewen; Jose, Anup; Kireev, Vassili; Lai, Kang Wei; Pham, Hiep; Turker, Didem; Wu, Daniel; Chang, Ken

doi:10.1109/ipec.2012.6522617

Cited by 2 publications

(4 citation statements)

References 5 publications

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“…4. It operates as a full wave rectifier as shown by its transfer function in (1). As opposed to many other peak detectors used in the literature, this design has the advantage of a differential output.…”

Section: B Peak Detectormentioning

confidence: 99%

“…As new communications applications are expanding, demands for wired serial communication is continuously increasing, and many advancements and new designs of transceivers are seen in the literature that can support multiple standards and protocols including SATA, PCI Express (PCIe), XAUI, LVDS, Interlaken and Infiniband protocols [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

“…This scaling proved better performance mainly in terms of lower power consumption. Compared to 40nm process, power consumption was reduced by 50% for similar performance [1]. Therefore a 28nm LOS detector is desirable.…”

Section: Introductionmentioning

confidence: 99%

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A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

Kawar

Abugharbieh

Al-Akel

et al. 2014

2014 IEEE International Conference on IC Design &Amp; Technology

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This paper presents a 10 Gbps loss of signal (LOS) detector for high-speed AC-coupled serial transceivers. The detector is designed in 28nm CMOS and is capable of operating with a 29.5mV internal eye opening and a 67mV external eye opening at the input pads. It consumes 69uW from a 0.9V supply at 10 Gbps and properly asserts an LOS state in 6.8 nsec. A novel comparator topology, which is a part of the LOS circuit, is also presented. It compares a differential input to a differential reference voltage. Design and layout were implemented using Synopsys Custom Designer with 28nm CMOS device models. The LOS detector can reduce power consumption and bit error rate (BER) of serial transceivers.

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Section: B Peak Detectormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

Kawar

Abugharbieh

Al-Akel

et al. 2014

2014 IEEE International Conference on IC Design &Amp; Technology

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“…To relax these challenges, several new methods are proposed. Firstly, as to the adaptation for continuous time equalization (CTLE), there are self-slope [6,16], spectrum-balancing [17], eye-opening monitor [18], edge-detected based [19], data level statistics [20], SS-LMS [21,22] and other methods. The methods based on spectrum-balancing and self-slope have the advantages of fast adjustment speed and continuous adjustment but poor adaptability [23].…”

Section: Introductionmentioning

confidence: 99%

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

Chen

Cai

Zhong

et al. 2023

IEICE Electron. Express

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In this work, a high-speed four-channel 0.8-6Gb/s wireline receiver was reported. Based on spectrum-balancing (SB) equalizer and slicer amplitude attenuator, it can be automatically adjusted to the most suitable state, avoiding the underbalanced or over-balance caused by amplitude mismatch. Moreover, a first-order semi-digital dual-loop clock and data recovery circuit (SDDCDR) with a high-speed digital loop filter (DLF) is also integrated to simplify the structure and improve the tracking ability of frequency offset. The prototype was fabricated on a 130nm CMOS process with a core area of 0.38 mm 2 for a single lane, consuming 97.3mW power at a 1.2V supply and tracking a 6966ppm frequency offset. In a 3m-cable test environment, the receiver sinusoidal jitter tolerance at high frequency is better than 0.22UI when 6Gb/s.

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A low-power 6.6-Gb/s wireline transceiver for low-cost FPGAs in 28nm CMOS

Cited by 2 publications

References 5 publications

A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

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