A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques

Nakagawa, Toshio; Izumi, Shintaro; Yanagida, Koji; Kitahara, Yoshinori; Yoshimoto, Shusuke; Umeki, Yohei; Mori, H.; Kuwabara, Hiroto; Kawaguchi, Hiroshi; Kimura, Hiromitsu; Marumoto, Kyoji; Fuchikami, Takaaki; Fujimori, Yoshikazu; Yoshimoto, Masahiko

doi:10.1109/iscas.2015.7169294

Cited by 1 publication

(1 citation statement)

References 10 publications

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“…Fig. 11 shows the vital sensor LSI for wearable healthcare applications [7], which consists of an electrocardiogram (ECG) sensor, the 32-bit CPU core with NVFF, and a 16-Kbyte FEbased non-volatile memory (NVRAM) [8] for data and instruction. Because the frequency range of vital signals is low, both the standby power reduction and sleep time maximization is important to system level power reduction.…”

Section: A Design Flowmentioning

confidence: 99%

A ferroelectric-based non-volatile flip-flop for wearable healthcare systems

Izumi

Kawaguchi

Yoshimoto

et al. 2015

2015 15th Non-Volatile Memory Technology Symposium (NVMTS)

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The low-power FE-based NVFF is developed by reduction of FE capacitor size. In the proposed NVFF, coupled FE capacitors with complementary data storage are introduced. The use of complementarily stored data in coupled FE capacitors achieves 88% FE capacitor size reduction while maintaining a wide read voltage margin of 240 mV (minimum) at 1.5 V, which results in 2.4 pJ low access energy with 10-year, 85 C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 s for 10-year data retention, and 170 ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. As a design example, the proposed NVFF is applied to 32-bit CPU in a vital sensor LSI for wearable healthcare applications. The vital sensor LSI consists of an electrocardiogram (ECG) sensor, the 32-bit CPU core with NVFF, and a 16-Kbyte FE-based non-volatile memory (NVRAM) for data and instruction. Because the frequency range of vital signals is low, both the standby power reduction and sleep time maximization is important to system level power reduction. Its standby current can be cut when the state of CPU core transits to deep sleep. Then the data in the memory and register values of CPU core in the NVFF are stored sequentially to ferroelectric capacitors. The implementation result demonstrates that 87% of total power dissipation during measurement of the heart rate can be reduced with 64% area overhead using 130-nm CMOS with Pb(Zr,Ti)O 3 (PZT) thin films.

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Section: A Design Flowmentioning

confidence: 99%