A Low Power 90nm Technology based CMOS Digital Gates with Dual Threshold Transistor Stacking Technique

Abstract

Scaling of transistor features sizes has improves performance, increase transistor density and reduces the power consumption. A chip's maximum power consumption depends on its technology as well as its implementation. As technology scales down and CMOS circuits are powered by lower supply voltages, leakage current becomes significant. static power is becoming the predominant source of energy waste. To create methodologies that support efficient designs, good performance, lower costs in the era of low power, is up to the design, EDA community . As the threshold voltage is reduced due to scaling, it leads to increase in sub threshold leakage current and hence increase in static power dissipation. This paper presents performance analysis of inverter using conventional CMOS, stack and dual threshold transistor stacking techniques. The performance analysis of inverter were analyzed in 90nm technology using Cadence virtuoso environment. The use of dual threshold voltages can significantly reduce static power dissipated in CMOS VLSI circuits.

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

“…However, introducing the third parameter of power dissipation made the designers to change the flow as shown fig 1. In CMOS VLSI circuits, power dissipation is basically due to the three important and major components: dynamic, static and short circuit.…”

“…P (switching)= C pd x V x F i (1) Where Fi is input signal frequency, Cpd dynamic power dissipation capacitance, V is the supply voltage. Due to the growing demand of battery operated devices, the power consumption has become a vital and major problem of integrated circuit designer.…”

“…The size of sleep transistor is reduced. The sleep transistors are designed as a high threshold voltage [1]. Fig.…”

“…The leakage through two series OFF transistor is much lower than that of single transistor be-cause of stack effect [4]. An effective way to reduce leakage power in active mode is stacking of transistor [1].…”