CALPAN: Countermeasure against Leakage Power Analysis attack by normalized DDPL

Padmini, C.; Ravindra, J. V. R.

doi:10.1109/iccpct.2016.7530142

Cited by 6 publications

(7 citation statements)

References 20 publications

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“…In [105], CPA with Hamming distance model (HDM) is conducted on the Sbox box output of triple data encryption standard (3DES) on a 32bit central processing unit smart card and the whole 112 key bits of 3DES are recovered with moderate effort, which is around 80,000 power traces. Pongaliur et al [93] have coined a three-phase attack [87] AES S-box area and power overhead (n-inverters, 2n-NAND gates, n-XOR gates for a n-input S-box circuit) power balanced circuits [77] serpent S-box -50% decrease in PBC value for LDPA compared to CMOS normalised DDPL [78,79] 2 model for SCA in sensor networks and have presented taxonomy of the same. They have proposed a new technique, called process obfuscation, which can be used as a countermeasure for a variety of SCAs on sensor nodes.…”

Section: Sca On Edge Nodesmentioning

confidence: 99%

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Survey on power analysis attacks and its impact on intelligent sensor networks

Shanmugham

Paramasivam

2018

IET wirel. sens. syst.

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Smart or intelligent sensors are integrated physical units embedded with sensors, processors, and communication devices. The sensors also known as edge nodes form the lower-most tier in the internet of things architecture. These devices rely on cryptographic technique to ensure 'root of trust' for the users. The implementation attacks namely side-channel attacks (SCAs) pose a dangerous threat for the cryptographic implementation in the edge nodes since the attacks are undetectable by nature. Among the different categories of SCAs proposed in the literature, power analysis attacks (PAAs) are vastly studied and widely employed because it can be mounted with relatively inexpensive equipment. In this study, the different categories of PAAs along with the countermeasures are reviewed in detail. The impact of the SCA on the edge nodes is examined along with a case study on medical sensor nodes.

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Section: Sca On Edge Nodesmentioning

confidence: 99%

“…Normalised DDPL and DDPL with sleep transistors are proposed in [78, 79] to thwart LPA. The functionality is implemented in the pull down network with sleep transistors for efficient power management.…”

Section: Power Analysis Attacks (Paas)mentioning

confidence: 99%

Survey on power analysis attacks and its impact on intelligent sensor networks

Shanmugham

Paramasivam

2018

IET wirel. sens. syst.

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“…In recent years, first potential countermeasures against static power side-channel analysis (SPSCA) have been investigated [18][19][20][21][22][23][24][25][26]. Similar to the early situation in the field of DPA countermeasures, most of these approaches fall into the hiding category [2] and can be split into two major groups, randomization [18,[23][24][25] and equalization [19][20][21][22]26,27]. Randomization approaches aim to reduce the signal-to-noise ratio (SNR) by generating additional noise to bury the signal in (either on-demand or on a constant basis).…”

Section: Introductionmentioning

confidence: 99%

“…The latter are also known as balancing techniques and come in different flavors. Some are based on conventional standard cells [20]; others require custom cell design [22,26,27]. Some are specifically targeting Hamming weight dependencies [19,21]; others attempt to generally reduce the current variations depending on the input [20,22,26,27].…”

Section: Introductionmentioning

confidence: 99%

“…Some are based on conventional standard cells [20]; others require custom cell design [22,26,27]. Some are specifically targeting Hamming weight dependencies [19,21]; others attempt to generally reduce the current variations depending on the input [20,22,26,27]. Although most of the previously listed works only aim at reducing the data dependency to some extent, BSPL [27], or rather Balanced Static Power Logic , is the first attempt to fully remove the imbalance by design.…”

Section: Introductionmentioning

confidence: 99%

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Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

2021

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The imbalance of the currents leaked by CMOS standard cells when different logic values are applied to their inputs can be exploited as a side channel to recover the secrets of cryptographic implementations. Traditional side-channel countermeasures, primarily designed to thwart the dynamic leakage behavior, were shown to be much less powerful against this static threat. Thus, a special protection mechanism called Balanced Static Power Logic (BSPL) has been proposed very recently. Essentially, fundamental standard cells are re-designed to balance their drain-source leakage current independent of the given input. In this work, we analyze the BSPL concept in more detail and reveal several design issues that limit its effectiveness as a universal logic library. Although balancing drain-source currents remains a valid approach even in more advanced technology generations, we show that it is conceptually insufficient to achieve a fully data-independent leakage behavior in smaller geometries. Instead, we suggest an alternative approach, so-called improved BSPL (iBSPL). To evaluate the proposed method, we use information theoretic analysis. As an attack strategy, we have chosen Moments-Correlating DPA (MCDPA), since this analysis technique does not depend on a particular leakage model and allows a fair comparison. Through these evaluation methods, we show iBSPL demands fewer resources and delivers better balance in the ideal case as well as in the presence of process variations.

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Current Balancing Random Body Bias in FDSOI Cryptosystems as a Countermeasure to Leakage Power Analysis Attacks

Palma

Moll

2022

IEEE Access

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This paper identifies vulnerabilities to recently proposed countermeasures to leakage power analysis attacks in FDSOI systems based on the application of a random body bias. The vulnerabilities are analyzed and the relative difficulty to obtain the secret key, once the vulnerabilities are taken into account, are compared to the original proposals. A new countermeasure, based on a new body bias scheme, is then proposed. The new countermeasure is based on the equalization of asymmetries in static power consumption dependent on data being stored in registers implemented in FDSOI technology. The countermeasure's effectiveness is theoretically established through the development of a power model based on technological parameters, and further reinforced through numerical simulations of a dummy cryptosystem implementing part of an AES encrypting round.INDEX TERMS Body bias, correlation power analysis, countermeasures, cryptography, FDSOI, leakage power analysis, side-channel. I. INTRODUCTIONThe exploitation of power consumption of cryptographic circuits as a source of information and a means to retrieve the secret key has been extensively studied in the last two decades [1]. These so called Power Analysis Attacks (PAA) rely on asymmetries in power consumption that arise from differing circuit states subjected to the data being processed in intermediate stages of encrypting algorithms.Traditionally, PAA have mainly focused on the dynamic power consumption of cryptographic circuits to derive statistical models of power consumption based on the data being processed. These models of power consumption allow the testing of secret key hypothesis with a minimum setting and quick computation.PAA traditionally rely on statistical metrics, namely, the Difference of Means or the Pearson Correlation Coefficient (PCC) [2], to test secret key hypothesis given a correct power model. Since power consumption is dependent on processed data which is, in turn, dependent on the secret key, the power consumed by a cryptographic circuit is highly correlated withThe associate editor coordinating the review of this manuscript and approving it for publication was Junggab Son .

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CALPAN: Countermeasure against Leakage Power Analysis attack by normalized DDPL

Cited by 6 publications

References 20 publications

Survey on power analysis attacks and its impact on intelligent sensor networks

Survey on power analysis attacks and its impact on intelligent sensor networks

Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

Current Balancing Random Body Bias in FDSOI Cryptosystems as a Countermeasure to Leakage Power Analysis Attacks

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