A low power and high density cache memory based on novel SRAM cell

Abstract

Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell, respectively.

SEU hardened layout design for SRAM cells based on SEU reversal

“…The area rate of static random access memory (SRAM) in advanced integrated circuits (ICs) becomes larger and larger [1,2]. However, the device size and the supply voltage scale with the technology progress, which decrease the critical charge and increase the rate of single event upset (SEU).…”