A Low Power and Low Noise Voltage-Controlled Oscillator in 28-nm FDSOI Technology for Wireless Communication Applications

Khan, Abdul Rahman; Cardenas, Jaime; Chen, Li; Khan, Muhammad R.; Qureshi, Aqeel A.

doi:10.1109/ccece.2019.8861796

Cited by 3 publications

(2 citation statements)

References 15 publications

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“…Based on the above data, the calculated FOM value of the LC VCO in this design is 185 dB. The results of the comparison between the calculated FOM value in this work and the FOM value of VCOs in some references are given in Table 1; our FOM value is better than those of some references [25,26], and our f 0 is much higher than that of [27]; thus, the present study achieves a better trade-off between the f 0 and FOM value.…”

Section: Lc Pll Noisementioning

confidence: 60%

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

et al. 2021

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This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

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Section: Lc Pll Noisementioning

confidence: 60%

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

et al. 2021

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“…A practical oscillator serves as energy source in microwave systems, integrated antennas, Radio Detection and Ranging (RADAR), and satellite communication systems [6]. Voltage-controlled oscillators (VCOs) is commonly used because of the significant reduction in electrical power requirements in modern communication systems [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Negative resistance amplifier circuit using GaAsFET modelled single MESFET

et al. 2020

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Negative resistance devices have attracted much attention in the wireless communication industry because of their low cost, better performance, high speed, and reduced power requirements. Although negative resistance circuits are non-linear circuits, they are associated with distortion, which may either be amplitude-to-amplitude distortion or amplitude-to-phase distortion. In this paper, a unique way of realizing a negative resistance amplifier is proposed using a single metal-semiconductor field-effect transistor (MESFET). Intermodulation distortion test (IMD) is performed to evaluate the characteristic response of the negative resistance circuit amplifier to different bias voltages using the harmonic balance (HB) of the advanced designed software (ADS 2016). The results obtained are compared to those of a conventional distributed amplifier. The findings of this study showed that the negative resistance amplifier spreads over a wider frequency output with reduced power requirements while the conventional distributed amplifier has a direct current (DC) offset with output voltage of 32.34 dBm.

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Design of an Ultra Low-Power Tunable Ring VCO in 65 nm CMOS Technology for 2.9-4.5 GHz

Korkut,

Ergin,

Şişman

et al. 2023

2023 International Conference on Electrical, Communication and Computer Engineering (ICECCE)

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A Low Power and Low Noise Voltage-Controlled Oscillator in 28-nm FDSOI Technology for Wireless Communication Applications

Cited by 3 publications

References 15 publications

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

Negative resistance amplifier circuit using GaAsFET modelled single MESFET

Design of an Ultra Low-Power Tunable Ring VCO in 65 nm CMOS Technology for 2.9-4.5 GHz

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