2021
DOI: 10.3390/electronics10141686
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An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

Abstract: This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduc… Show more

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Cited by 7 publications
(3 citation statements)
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“…The CP uses two rail-to-rail operational amplifiers to reduce the drain-voltage fluctuations in the metal-oxide-semiconductor field-effect transistor (MOSFET) in the current supply, with the goal of mitigating the mismatch between the charge and discharge currents introduced by channel-length modulation [16]. Moreover, a ring VCO architecture is adopted to reduce the chip area and cost, while providing a broadband tuning range [17]. The PD and OD divide the frequency of the reference and output clocks, respectively, to expand the output frequency band of the PLL [18].…”
Section: Pll Circuit Implementationmentioning
confidence: 99%
“…The CP uses two rail-to-rail operational amplifiers to reduce the drain-voltage fluctuations in the metal-oxide-semiconductor field-effect transistor (MOSFET) in the current supply, with the goal of mitigating the mismatch between the charge and discharge currents introduced by channel-length modulation [16]. Moreover, a ring VCO architecture is adopted to reduce the chip area and cost, while providing a broadband tuning range [17]. The PD and OD divide the frequency of the reference and output clocks, respectively, to expand the output frequency band of the PLL [18].…”
Section: Pll Circuit Implementationmentioning
confidence: 99%
“…The VCO generates an output signal based on the input reference clock. VCOs used in PLL frequency synthesizers are commonly realized with LC ‐tanks [1, 2] or ring topologies [3, 4]. Generally, LC‐VCOs consist of an inductor L and voltage‐tunable capacitor C forming a parallel tank which oscillates at 12πLC$\frac{1}{{2\pi \sqrt {LC} }}$.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, the conventional design of VCO is focused on noise suppression of the power supply. A low-dropout regulator (LDO) is a common method to provide high-quality power supply to the VCO [6,7].…”
Section: Introductionmentioning
confidence: 99%