A Low-Power CMOS Class-E Chireix RF Outphasing Power Amplifier for WLAN Applications

Abstract

This paper describes the design and implementation of a low-power CMOS class-E Chireix RF outphasing power amplifier (PA) for WLAN applications. The proposed circuit is based on cascode class-E topology with two-stage structure and Chireix power combiner with a floating load. This class-E topology adopts self-biased technique and current-reused technique that avoids using thick-oxide transistors and can enhance the driving ability and power gain. Additionally, the Chireix combiner can reduce the loss of power and improve the efficiency by avoiding the use of isolation resistance. With a 2.5 V power supply, the realized prototype achieved 21.4 dBm of maximum output power and 29.9 % of average power-added efficiency (PAE) at 2.4 GHz. When operated for minimum input levels at 2.5 V, it reached 38.8 dB power gain. For a WLAN OFDM signal with 20 MHz, the error vector magnitude of 3 % is achieved with peak drain efficiency of 62 %. Moreover, the outphasing power amplifier is fully integrated with TSMC 0.18-lm CMOS technology and the chip area including testing pads is 1.07 9 1.17 mm 2 .

RF Blocks for Biomedical Engineering

“…Their PAE was better than single-stage PA, which was 48.3% [14]. Another two-stage structure was used to lower power dissipation; but on the other hand, their PAE was dropped to 29.9% [15]. In this work, a new feedback-loop PA test circuit was simulated.…”