A low-power CMOS frequency synthesizer for GPS receivers

Yu, Yunfeng; Jian-lian, Yue; Shimao, Xiao; Zhuang, Haixiao; Ma, Can; Ye, Tianchun

doi:10.1088/1674-4926/31/6/065012

Cited by 4 publications

(1 citation statement)

References 8 publications

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“…Zhao Li et al [7] found that the optimal noise model for IGS reference station coordinate time series in China is not a single model, but has diversity. Yunfeng Tian et al [8] analyzed the characteristics of the correlated noise in the position time series of the GPS reference stations of the China Crustal Movement Observation Network, and found that in addition to the Flicker Noise, the correlated noise in the east component of about 50% stations can be described by FOGMRW model.…”

Section: Introductionmentioning

confidence: 99%

Establishment of optimal noise model for GNSS time series in Zhejiang

Yang

Gong

et al. 2023

International Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2023)

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With the continuous improvement of GNSS observation technology, and the accumulation of decades of observation data of GNSS observation stations such as IGS station, more in-depth analysis of GNSS coordinate time series can be carried out. GNSS coordinate time series can be described as the sum of actual signal and noise. Modeling and correcting the noise in GNSS coordinate time series can play a good role in weakening the error in GNSS data. In this paper, the optimal noise model of the coordinate time series of 18 CORS stations in Zhejiang region is established. The experimental results show that the noise models of the coordinate time series of CORS stations in Zhejiang are diverse, and the N, E, U components show different noise characteristics, which is different from the existing models. The existing Flicker Noise + White Noise (WN+FN) combination model can only represent the optimal noise characteristics of 29.63% station components; When analyzing the anniversary amplitude, ignoring the selection of the noise model will lead to the underestimation of the anniversary amplitude. Compared with WN+FN, the impact of different complex noise models on the velocity is negligible, but the impact on the velocity uncertainty of each component of the station is large. Using only a single noise model will cause the underestimation of the station velocity uncertainty.

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Section: Introductionmentioning

confidence: 99%

Establishment of optimal noise model for GNSS time series in Zhejiang

Yang

Gong

et al. 2023

International Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2023)

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A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

Zhang,

Geng,

et al. 2024

J. Semicond.

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A frequency servo system-on-chip (FS-SoC) featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium (Cs) atomic clocks. The proposed power stabilization loop (PSL) technique, incorporating an off-chip power detector (PD), ensures that the output power of the FS-SoC remains stable, mitigating the impact of power fluctuations on the atomic clock's stability. Additionally, a one-pulse-per-second (1PPS) is employed to synchronize the clock with GPS. Fabricated using 65 nm CMOS technology, the measured phase noise of the FS-SoC stands at −69.5 dBc/Hz@100 Hz offset and −83.9 dBc/Hz@1 kHz offset, accompanied by a power dissipation of 19.7 mW. The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7 × 10−11 with 1-s averaging time.

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A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver

et al. 2012

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This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13 m CMOS technology. The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter. A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration. Pulse-swallow topology with a multistage noise shaping † modulator is adopted in the frequency divider design. The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes. Measurement results show that the phase noise of the synthesizer achieves-91.3 dBc/Hz and-117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset, separately. The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm 2 .

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A low-power CMOS frequency synthesizer for GPS receivers

Cited by 4 publications

References 8 publications

Establishment of optimal noise model for GNSS time series in Zhejiang

Establishment of optimal noise model for GNSS time series in Zhejiang

A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver

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