A low-power CMOS readout IC design for bolometer applications

Abstract

A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (≥ 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 µm 2 pixel sizes in development. The prototype has been designed and fabricated in 0.25-µm SiGe:C BiCMOS process.

Physical device modeling of Si/Si1-xGex multi-quantum well detector to optimize Ge content for higher thermal sensitivity

“…12 Inevitably, a detector with larger R exhibits higher Johnson Noise, as well as endures a great deal of challenge for a readout design. 13 As a matter of fact, (1) and (4) renders the critical design constraint and trade-off in terms of T CR and R. From a detector point of view, in order to improve the over all Signal-to Noise ratio, the Ge content in a well must be optimized in a way to improve T CR whilst keeping R at moderate value. For a Si 1−x Ge x MQW device, R can be reduced by selectively and carefully optimized doping in the MQW regions such that E F,p shifts close to the valence band edge of the well without losing the effective barrier height and thus T CR is not deteriorated.…”