A low-power Content-Addressable Memory based on clustered-sparse networks

Abstract

Abstract-A low-power Content-Addressable-Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The proposed architecture is based on a recently developed clustered-sparse-network using binary-weighted connections that on-average will eliminate most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared to that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. A 0.13µm CMOS technology was used for simulation purposes. The energy consumption and the search delay of the proposed design are 9.5%, and 30.4% of that of the conventional NAND architecture respectively with a 3.4% higher number of transistors.

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

“…We propose to replace all the arithmetical-integer computations by logical equations, that is, to define a full binary neural network model. This property, which has first been introduced in Chavet et al [2012] and later partially used to design content addressable memories in Jarollahi et al [2013], is detailed in this section. The proposed fully binary model allows removing both the WTA step and achieving the same performances as the enhanced GBNN model [Gripon and Berrou 2012].…”

Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories

“…The index (position) of the selected bits for extraction are consistent in all inputs. In databases, where a field receives inputs with high degrees of similarity, an SCN-based associative memory still generates the correct results, as shown in [10]. However, higher number of pattern similarities result in the generation of a larger number of output search results that include the desired ones.…”

Improving Sparse Associative Memories by Escaping from Bogus Fixed Points

“…The same authors implement SUM-OF-MAX in [21] and runs 1.9× faster than [20], since bitwise operations are used in place of a resource-demanding module required by SUM-OF-SUM. In [22], the same group of authors also develop a content addressable memory using GBNNs which saves 90% of the energy consumption. Larras et al [23] implement an analog version of the network which consumes 1165× less energy but is 2× more efficient both in the surface of the circuit and speed, compared with an equivalent digital circuit.…”