A Low-Power Digit-Based Reconfigurable FIR Filter

Chen, Kuan‐Hung; Chiueh, Tzi‐Dar

doi:10.1109/tcsii.2006.875373

Cited by 140 publications

(107 citation statements)

References 15 publications

Supporting

Mentioning

107

Contrasting

Order By: Relevance

“…For example, a FIR filter implemented by Mahesh et al [2] using programmable shift method (PSM) and Constant shift method (CSM) [8] [11]. Park [3] also implemented a FIR filter based on distributed arithmetic structure in direct form and transpose form structures.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Block Based Transpose Form FIR Filter

Krishna¹,

Narasimhulu²,

Prasad³

2018

IJCA

View full text Add to dashboard Cite

The transpose form configuration of Finite impulse response filter (FIR) does not support for block based processing se form FIR filter architecture is optimized and implemented. The basic Data Flow Graph (DFG) of transpose form FIR filter is converted into block based DFG and retiming is inserted in the DFG for low power consumption, reduced area and minimal delay. The generalized mathematical formulation is done for the retimed block based transpose form FIR filter and it is implemented with the block size of 4 for the filter length of 16 using Verilog Hardware Description Language (HDL). Later, it is synthesized using CADENCE-RTL compiler in TSMC 45nm CMOS library and power, area and delay reports are generated. The obtained results are compared with the few existing structures.

show abstract

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Block Based Transpose Form FIR Filter

Krishna¹,

Narasimhulu²,

Prasad³

2018

IJCA

View full text Add to dashboard Cite

show abstract

“…The frequency response of an FIR filter can be changed by completely changing its coefficients or by modifying the impulse response using various operations. In the programmable digital filters [1]- [4], the desired frequency responses are obtained by updating all the filter coefficients which are stored in the memory. This is a very simple approach, and in general, the variable coefficient filters are optimum in a sense that the filter length for the particular frequency response specifications is the minimum.…”

Section: Introductionmentioning

confidence: 99%

Design and FPGA Implementation of Variable Cutoff Frequency Filter based on Continuously Variable Fractional Delay Structure and Interpolation Technique

Dhabu

Vinod

2015

International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems

View full text Add to dashboard Cite

Abstract-This paper presents the design and FPGA implementation of interpolated continuously variable fractional delay structure based filter (ICVFD filter) with fine control over the cutoff frequency. In the ICVFD filter, each unit delay of the prototype lowpass filter is replaced by a continuously variable fractional delay (CVFD) element proposed in this paper. The CVFD element requires the same number of multiplications as that of the second-order fractional delay structure used in the existing fractional delay structure based variable filter (FDS based filter), however it provides fractional delays corresponding to the higher-order fractional delay structures. Hence, the proposed ICVFD filter provides wider cutoff frequency range compared to the FDS based filter. The ICVFD filter is also capable of providing variable bandpass and highpass responses. We use two-stage approach for the FPGA implementation of the ICVFD filter. First, we use pipelining stages to shorten the critical path and improve the operating frequency. Then, we make use of specific hardware resource, i.e. RAM-based Shift Register (SRL) to further improve the operating frequency and resource usage.Keywords-FPGA implementation, fractional delay structure based filter, reconfigurable digital filter, variable cutoff frequency filter.

show abstract

“…Multi-channel digital up converters (DUC) and digital down converters (DDC) are broadly used to implement the digital front end (DFE) of various standards such as Long-Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), Intelsat Earth Station Standards (IESS), and their software defined radio applications [1,2,3,4]. A single channel DUC/DDC has intrinsically two separate channels for in-phase and quadrature (I/Q), thus N-channel DUC/DDC has 2N equivalent channels.…”

Section: Introductionmentioning

confidence: 99%

A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

Park

2015

IEICE Electron. Express

View full text Add to dashboard Cite

This paper proposes a low-cost implementation of a multichannel FIR filter on FPGA, where each channel can have variable bandwidth and coefficients. New structures of the tapped-delay line and the coefficient bank unit based on time-division multiplexing are proposed. Pipelined adder tree is used to expedite the filtering process without disturbing generation of control signals for multi-channel data access. From implementation results, it is found that the proposed 39-tap FIR filter involves 32% less number of slice registers as well as 65% less number of DSP blocks than the Xilinx FIR Core 5.0, and also supports variable bandwidth.

show abstract

A Low-Power Digit-Based Reconfigurable FIR Filter

Cited by 140 publications

References 15 publications

Design and Implementation of Block Based Transpose Form FIR Filter

Design and Implementation of Block Based Transpose Form FIR Filter

Design and FPGA Implementation of Variable Cutoff Frequency Filter based on Continuously Variable Fractional Delay Structure and Interpolation Technique

A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

Contact Info

Product

Resources

About