2015
DOI: 10.1109/tcsii.2015.2455354
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A Low-Power Edge Detection Image Sensor Based on Parallel Digital Pulse Computation

Abstract: An all digital low-power CMOS edge detection image sensors array is presented. Each pixel contains a voltagecontrolled ring oscillator to achieve low power and cost efficient digital only edge detection. While conventional edge detection methods require high computing power as well as large chip area to process intensity maps, this work implements all-digital parallel processing algorithm that detects differences between neighboring pixel pairs on-chip, hence reducing the aforementioned power and cost overhead… Show more

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Cited by 18 publications
(11 citation statements)
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“…After scanning multiple rows simultaneously and calculating horizontal, vertical, and diagonal edges, the area of the digital circuit was quite large, resulting in low resolution, low conversion speed, and high power consumption. In [ 6 ], the analog signal was directly converted to the frequency domain signal at the same time that the mask technique was applied to reduce power consumption and achieve high-speed conversion. Thus, the resolution was quite low, prohibiting its use for high-resolution CIS applications.…”
Section: Resultsmentioning
confidence: 99%
See 2 more Smart Citations
“…After scanning multiple rows simultaneously and calculating horizontal, vertical, and diagonal edges, the area of the digital circuit was quite large, resulting in low resolution, low conversion speed, and high power consumption. In [ 6 ], the analog signal was directly converted to the frequency domain signal at the same time that the mask technique was applied to reduce power consumption and achieve high-speed conversion. Thus, the resolution was quite low, prohibiting its use for high-resolution CIS applications.…”
Section: Resultsmentioning
confidence: 99%
“…In this process, the difference in the output code of data between adjacent columns that To implement the edge-detection process in a conventional CIS, a row buffer with several rows has been used to design a 3 × 3 mask circuit in a circuit, which greatly increased the layout size and power consumption of the entire block [5]. Additionally, a global shutter method through an in-pixel ADC has been used [6], which requires a different type of pixel design. This in-pixel ADC decreases the pixel's fill factor, thus greatly increasing the unit cell size of the pixel.…”
Section: Proposed Algorithm For Edge Detectionmentioning
confidence: 99%
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“…This technique limits the image processing speed and requires many memory blocks [ 6 , 7 ]. Therefore, the conventional lane detection method results in a high-power consumption when used in high-speed cars with high processing speeds [ 8 , 9 ]. Figure 1 b shows a system flow chart of the proposed edge detection system.…”
Section: Introductionmentioning
confidence: 99%
“…The edge of the image contains important structural information and is considered as the first step of image analysis and pattern recognition. Because by edge detection, the size of image data can be reduced to a size more suitable for image analysis [1][2][3]. The execution of tasks after edge detection, such as image segmentation [4,5], boundary detection [6,7], defect classification [8,9,10], and image registration [11,12], all depend on the edge information.…”
Section: Introductionmentioning
confidence: 99%