A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS

A two-point tuning VCO with switchable secondary tuning gain K VCO2 is designed in 65nm CMOS for a two-point modulation PLL-based phase modulator that is to serve as phase-modulating part of a quad-band GSM/GPRS/EDGE polar transmitter. The two-point tuning VCO employs two varactor banks for dual tuning capability. The second varactor bank is a differentially tuned structure and its gain K VCO2 is switchable to minimize its variation for maintaining optimum second-point modulation gain. Fabricated in 65nm CMOS, the VCO draws 8 mA from 2 V supply. It covers the 2930 -4150 MHz. The phase noise is -142dBc/Hz at 10MHz offset for 3.9 GHz output frequency. The silicon area of the VCO and accompanying dividers is 810 x 600 Pm 2 .

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“…The bandwidth of the phase modulation signal of EDGE reaches almost 800 kHz [7]. With design margin, the maximum FM BW is set to 2 MHz.…”

Section: Switchable K Vco2mentioning

confidence: 99%

“…Polar transmitter is an effective transmitter architecture that can support multi-modulation format [5]- [7]. It decomposes the baseband data into amplitude-modulation (AM) part and phase-modulation (PM) part, modulates the AM and PM data by separate modulation circuitry, and finally sends out the combined output.…”

Section: Introductionmentioning

confidence: 99%

A two-point tuning LC VCO with minimum variation of K<inf>VCO2</inf> for quad-band GSM/GPRS/EDGE polar transmitter in 65-nm CMOS

Son

Kim

Shin

2013

2013 International SoC Design Conference (ISOCC)

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“…Poor linearity of the VCO affects the EVM and out-of-band phase noise performances, but calibrating the VCO nonlinearity over process and temperature variations is very challenging in practice [1], [2]. The all-digital PLL (ADPLL) design with a digitally-controlled oscillator (DCO) offers a robust way of calibrating the DCO gain [3], [4], but the DCO nonlinearity calibration could require complex algorithm with a long background calibration time [4].…”

Section: Introductionmentioning

confidence: 99%

A 2 GHz 2 Mb/s Semi-Digital <formula formulatype="inline"><tex Notation="TeX">$2^{+}$</tex></formula>-Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>m CMOS

Rhee

Wang

2015

IEEE Microw. Wireless Compon. Lett.

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A 2 GHz two-point modulator which has a separate high-pass control for DCO modulation is implemented in 0.18 m CMOS. The proposed modulator with the two-path DCO modulation enables a flexible gain partition for the high-pass and low-pass modulation paths within the DCO and relaxes the DCO nonlinearity with 1-b modulation and embedded finite-impulse response (FIR) filtering. A semi-digital PLL with another FIR filtering in the low-pass modulation enhances PLL linearity with a hybrid loop control. The proposed semi-digital modulator achieves 2.03% RMS EVM with 2 Mb/s GFSK modulation, dBc/Hz phase noise at 3 MHz offset, and dBc reference spur.

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“…Polar transmitters based on the envelope-elimination restoration (EER) technique have been widely adopted as they are promising for multi-mode and power-efficient transceiver systems [1]- [4]. Fig.…”

Section: Introductionmentioning

confidence: 99%

A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters

Shen

Rhee

Wang

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a ΔΣ modulated digital power amplifier (DPA) with a finite-impulse response (FIR) filter for wireless body area network (WBAN) applications. The proposed DPA utilizes a 1-bit second-order ΔΣ modulator to avoid nonlinearity problem of the multi-level quantization and achieve better quantization noise performance than the first-order modulator. The time-interleaving operation inherently provided by the embedded FIR filter mitigates the mismatching effect of PA cells. The proposed architecture not only improves the outof-band noise performance but also reduces AM-AM and AM-PM distortions. The proposed ΔΣ DPA is implemented in 65nm CMOS. Simulation results show that it can achieve good out-ofband noise performance with the maximum output power of 6dBm and maximum power-added efficiency of 45%.978-1-4799-8391-9/15/$31.00 ©2015 IEEE

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A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS

Cited by 43 publications

References 39 publications

A two-point tuning LC VCO with minimum variation of K<inf>VCO2</inf> for quad-band GSM/GPRS/EDGE polar transmitter in 65-nm CMOS

A two-point tuning LC VCO with minimum variation of K<inf>VCO2</inf> for quad-band GSM/GPRS/EDGE polar transmitter in 65-nm CMOS

A 2 GHz 2 Mb/s Semi-Digital <formula formulatype="inline"><tex Notation="TeX">$2^{+}$</tex></formula>-Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>m CMOS

A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters

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A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS

Cited by 43 publications

References 39 publications

A two-point tuning LC VCO with minimum variation of K<inf>VCO2</inf> for quad-band GSM/GPRS/EDGE polar transmitter in 65-nm CMOS

A two-point tuning LC VCO with minimum variation of K<inf>VCO2</inf> for quad-band GSM/GPRS/EDGE polar transmitter in 65-nm CMOS

A 2 GHz 2 Mb/s Semi-Digital <formula formulatype="inline"><tex Notation="TeX">$2^{+}$</tex></formula>-Point Modulator With Separate FIR-Embedded 1-Bit DCO Modulation in 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>m CMOS

A digital power amplifier with FIR-embedded 1-Bit high-order &#x0394;&#x03A3; modulation for WBAN polar transmitters

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A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters