A low-power high-performance voltage sense amplifier for static RAM and comparison with existing current/voltage sense amplifiers

Divya, .; Mittal, Poornima

doi:10.1007/s41870-022-00916-x

Cited by 7 publications

(2 citation statements)

References 24 publications

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“…Therefore, it is highly critical for performance of cache memory. It helps in determining the operational frequency, power consumption, and minimum operating point, for cache memory [4,5]. The essential performance parameters for SA includes -minimum differential input voltage, sensing delay, and power consumption [6,7].…”

Section: Introductionmentioning

confidence: 99%

A latch-based sense amplifier with improved performance for single ended SRAM application

Rawat

Mittal

2023

Phys. Scr.

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The growing processing load and decreasing technology node has augmented the need for single ended memory. Consequently, generating requirement for a single ended sense amplifier for ease of integration with single ended memory. Therefore, this paper presents a single bitline based latch type sense amplifier. It is designed at feature size of 32 nm and its performance is evaluated at 1 V supply, with the environment temperature at 27 ⁰C. It is analyzed for its output waveform, delay, variability tolerance, and area occupancy. The ON current for the proposed sense amplifier is 1.2 uA, while the OFF current is 10 nA. The ON current for proposed sense amplifier is is 0.18, 0.43, and 0.88 times higher than SA-2, SA-5, and SA-6 respectively. While, its OFF current is lowest with the exception of SA-3 at 9 nA. Also, the delay for the proposed sense amplifier is minimal at 0.77 ns in comparison to other topologies. The SA-1, SA-2, SA-5, and SA-6 are 3.9, 2.8, 3.7, and 0.3 times slower than SA-P, thereby deeming its operation faster than others. The reliability for the proposed circuit is evaluated using process corner analysis for all performance parameters.

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Section: Introductionmentioning

confidence: 99%

A latch-based sense amplifier with improved performance for single ended SRAM application

Rawat

Mittal

2023

Phys. Scr.

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“…As the V DD -V TH decreases, noise margin significantly degrades thus, making the circuit susceptible to operational failure [16]. Furthermore, because random dopant fluctuations and random PVT variations are so common in the sub-micrometre domain, the stability of the design has been significantly compromised [17,18]. As a result, cache memories, comprised of SRAM cells, are probably more susceptible to these failures [19].…”

Section: Introductionmentioning

confidence: 99%

A single ended, single port configuration based 9 T SRAM cell for stability enhancement

Singhal,

Rawat,

Mittal

et al. 2023

Phys. Scr.

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The growing demand for power efficient devices and high-density memories has pushed researchers to develop low power SRAMs. The main objective for these researches is to reduce power consumption and enhances battery life and scaling of technology node. Consequently, in this paper a 9T SRAM bit cell with enhanced stability and single ended, single port configuration is proposed. The cell is designed and simulated at 180 nm technology node with a voltage supply of 1V. The cell proposed has low power consumption owing to single bitline, higher read stability due to isolated read port, better write margin due to disconnected feedback connection and resistant to soft errors because of half select disturbance free architecture. To assess the performance of the proposed cell its performance is compared against existing 6T, 8T, 9TST, SB 9T, TRD 9T, and NTV 9T bit cells. The HSNM (RSNM) and WM values for the proposed cell are equal to 364 mV and 368 mV respectively. The cell is designed to be half select disturbance free and supports bit interleaving. The reliability of the proposed cell is further analysed for local, global and temperature variation. While, the area footprint for the cell is 24.91 µm2.

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A Comprehensive Review to Investigate the Effect of Read Port Topology on the Performance of Different 7 T SRAM Cells

Rawat,

Mittal

2024

Lecture Notes in Electrical Engineering

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A low-power high-performance voltage sense amplifier for static RAM and comparison with existing current/voltage sense amplifiers

Cited by 7 publications

References 24 publications

A latch-based sense amplifier with improved performance for single ended SRAM application

A latch-based sense amplifier with improved performance for single ended SRAM application

A single ended, single port configuration based 9 T SRAM cell for stability enhancement

A Comprehensive Review to Investigate the Effect of Read Port Topology on the Performance of Different 7 T SRAM Cells

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