A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications

Abstract

Ring oscillator (RO)-based physical unclonable function (PUF) is resilient against noise impacts, but its response is susceptible to temperature variations. This paper presents a low-power and small footprint hybrid RO PUF with a very high temperature stability, which makes it an ideal candidate for lightweight applications. The negative temperature coefficient of the low-power subthreshold operation of current starved inverters is exploited to mitigate the variations of differential RO frequencies with temperature. The new architecture uses conspicuously simplified circuitries to generate and compare a large number of pairs of RO frequencies. The proposed ninestage hybrid RO PUF was fabricated using global foundry 65-nm CMOS technology. The PUF occupies only 250 µm 2 of chip area and consumes only 32.3 µW per challenge response pair at 1.2 V and 230 MHz. The measured average and worst-case reliability of its responses are 99.84% and 97.28%, respectively, over a wide range of temperature from −40 to 120 • C.Index Terms-Hardware security, physical unclonable function (PUF), process variation, ring oscillator (RO), temperature stability.

Lightweight signature scheme to protect intellectual properties of Internet of things applications in system on chip field-programmable gate arrays

“…The low-power hybrid RO PUF is implemented in 65 nm, and its power is measured in µW, and it is homogeneous. However, the proposed model is implemented in SoC FPGA, which is 28 nm with heterogeneous PUF; hence, its power and area vary and are uncomparable with those in [28]. The proposed model is executed for 10,000 iterations, and a specific sample of 500 iterations has been selected for two different chips, and its HD and KEY values are fixed, based on Figures 8 and 9.…”

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

“…It has to be noted that the IoT devices are mostly battery-powered embedded devices and operate in low-frequency ranges. Meanwhile, all PUF cells presented in [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] undergo high-power consumption and voltage ramp-up time adaptation for a reliable PUF circuit [33]. To address for low-power and stable PUF security profiles, the low-power technique of the adiabatic switching principle [34] has been adopted in SRAM style PUF cell design [33,35].…”

“…Finally, Section 5 concludes the research findings of this work. The PUF security metrics (the stability, the reliability, and the uniqueness) and the low power requirement have triggered enormous studies at the PUF cell level, such as investigations on the arbiter PUF [16][17][18], ring-oscillator (RO) PUF [19][20][21][22][23][24], be-stable ring PUF [25], glitch PUF [26], dynamic random access memory (DRAM) PUF [27,28], and static random access memory (SRAM) PUF [29,30]. In addition, many studies on lowpower PUF circuits have been conducted, such as robust digital response and low-power current-based PUF [31], as well as the SRAM-based PUFs, over a wide range of supply voltages from the super-threshold voltage regime down to the near-threshold voltage (NTV) regime [32].…”

Pixelated Physical Unclonable Functions through Capillarity-Assisted Particle Assembly

“…Authentication is often enabled by means of alignment markers, which nonetheless always introduce a certain degree of mismatch between the original patterns and subsequent readouts. Small alignment deviations in fact lead to the input and the output images never being exactly the same and being prone to changes over time and mechanical/chemical damage. , These limitations have led to multiple efforts to optimize the robustness and stability of the available PUF systems by encapsulation, improved system design, , material development, response signal amplification, , and most commonly, improved evaluation methods. , …”