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Internet of Things (IoT) has enabled battery-powered devices to transmit sensitive data, while presenting high power consumption and security issues. To address these challenges, adiabatic-based physical unclonable functions (PUFs) offer a promising solution for low-power and secure IoT device applications. In this study, we propose a novel low-power two-phase clocking adiabatic PUF. The proposed adiabatic PUF utilizes a trapezoidal power clock signal with a time-ramped voltage to achieve an improved energy efficiency and reliable start-up PUF behavior. Static CMOS logic is employed to produce stable challenge-response pairs (CRPs) in the adiabatic mode. The pull-down network is designed to control the PUF cell to charge and discharge its output nodes with a constant supply current during secure key generation. The body effect of PMOS transistors, ambient temperatures, and CMOS process variations are investigated to examine the uniqueness and reliability of the proposed work. The proposed adiabatic PUF is simulated using 0.18 µm CMOS process technology with a supply voltage of 1.8 V. The uniqueness and reliability of the proposed adiabatic PUF are 49.82% and 99.47%, respectively. In addition, it requires a start-up power of 0.47 µW and consumes an energy of 15.98 fJ/bit/cycle at the reference temperature of 27 °C.

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Numerous articles and patents on the masking of logic gates in CMOS logic styles have been reported, however, less information is available with regards to comparing the single rail and dual-rail on masking input logic values. This paper investigates single-rail and dual-rail logic families that have been developed by the logic designers for secure logic implementations in cryptographic system. The novelty of this work is that we evaluate the dynamic logic and ditTerential logic for one-phase 2-inputs logic in adiabatic mode in SPICE simulation. We analyze the power consumption of logic circuit along 16 possible transitions of 2-inputs logic during one cycle. The power traces show that adiabatic ditTerentiai logic families are masking the input logic values, because they consume constant power during pre-charge and evaluation phases that enables the circuit to resist against power analysis attacks. Based on our results, we deduce that adiabatic ditTerentiailogic families are promising candidates for further development to obtain a far more robust secure logic for countermeasure against power analysis attacks in smart card. I. INT RODUCTIONPower analysis attacks have become a special threat for cryptanalysis algorithm designers, software developers and hardware engineers to maintain the security of secret key in cryptographic implementation, such as in smart card. During the past years, a lot of researches have been conducted on simple power analysis (SPA) and differential power analysis (DPA) [1,2] on mathematical algorithm level. The SPA is more focusing on the use of visual inspection techniques to identify relevant power fluctuations during cryptographic operations, hence it is vulnerable for attackers to identify the secret key by calculating the power consumption during cryptographic operations. DPA attacks are more advanced than SPA attacks in which they use the statical methods and digital processing techniques on large number of power consumption signals to reduce noise and strengthen the difference signals, so it will be obvious to distinguish between the logical zero and logical one. There was also an effort of Adi Shamir to protect smart card from two main attacks, such as DPA and SPA attacks by detaching two capacitors to smart card [3]. His work was to detach two capacitors to work as a power isolation element by switch control unit and four power transistors 978-1-4577-2166-3/111$26.00 ©2011 IEEE which are added to the smart card chip. To protect the secret keys during encryption and decryption execution of smart card from power analysis attackers, there are a lot of efforts to mask the secret keys on algorithm level and monitoring power consumption signals to withstand side channel attacks (SCA) of cryptographic systems [4]- [7].The fundamental issues of power analysis attacks on cryp tographic systems are closely related to electrical power consumption of hardware implementations. Regarding power consumption in cryptographic implementation such as smart card, logic design should be highly consider...