Low-Power Two-Phase Clocking Adiabatic PUF Circuit

Abstract

Internet of Things (IoT) has enabled battery-powered devices to transmit sensitive data, while presenting high power consumption and security issues. To address these challenges, adiabatic-based physical unclonable functions (PUFs) offer a promising solution for low-power and secure IoT device applications. In this study, we propose a novel low-power two-phase clocking adiabatic PUF. The proposed adiabatic PUF utilizes a trapezoidal power clock signal with a time-ramped voltage to achieve an improved energy efficiency and reliable start-up PUF behavior. Static CMOS logic is employed to produce stable challenge-response pairs (CRPs) in the adiabatic mode. The pull-down network is designed to control the PUF cell to charge and discharge its output nodes with a constant supply current during secure key generation. The body effect of PMOS transistors, ambient temperatures, and CMOS process variations are investigated to examine the uniqueness and reliability of the proposed work. The proposed adiabatic PUF is simulated using 0.18 µm CMOS process technology with a supply voltage of 1.8 V. The uniqueness and reliability of the proposed adiabatic PUF are 49.82% and 99.47%, respectively. In addition, it requires a start-up power of 0.47 µW and consumes an energy of 15.98 fJ/bit/cycle at the reference temperature of 27 °C.

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

“…The TPCA-PUF cell was implemented using SRAM-based circuit topology, and hence this study is claimed to be the first work in the literature employing FinFET-based SRAMtype PUF. Consequently, the previous reports of SRAM-based QUALPUF and TPCA-PUF [33,35] were re-simulated in the FinFET 45 nm process, as depicted in Figures 7-11, and the key performances are described in Table 2. From Figures 7-11, we can observe that the proposed FinFET-based TPCA-PUF demonstrated its superior performance (for both power and security metrics).…”

“…This means that if one cycle of the Vpc signal is 10 ns, then the second Cb signal has a 2.5 ns delay time compared to the first Cb signal. This delay time allows the challenge bits to flip the response signals right at the middle point of the idle/wait phase of the Vpc signals, and the challenge bits are perfectly flipped adiabatically, and as result of this, the energy is significantly reduced, as reported in [33].…”

“…It has to be noted that the IoT devices are mostly battery-powered embedded devices and operate in low-frequency ranges. Meanwhile, all PUF cells presented in [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] undergo high-power consumption and voltage ramp-up time adaptation for a reliable PUF circuit [33]. To address for low-power and stable PUF security profiles, the low-power technique of the adiabatic switching principle [34] has been adopted in SRAM style PUF cell design [33,35].…”

“…In this work, a novel study on FinFET-based SRAM PUF is presented. The previous work on two-phase clocking adiabatic PUF (TPCA-PUF) [33] cells is investigated using the dual-gate FinFET 45 nm process with 1.0 V nominal supply voltage. The uniqueness, reliability, and the BER of the proposed TPCA-PUF are compared with the QUALPUF [35] using the same process technology.…”

“…The proposed FinFET-based TPCA-PUF circuit topology is shown in Figure 4. The CMOS-based TCPA-PUF was proposed in [33], which is adiabatically operated in four phases (wait, evaluate, hold, and recover phases). It consists of a static CMOS inverter (P1 and N1), which plays a key role in charging and discharging the PUF cell semi-adiabatically using a trapezoidal power clock signal of Vpc and controlled by the Cb.…”