DPA resistance of charge-sharing symmetric adiabatic logic

Monteiro, Câncio; Takahashi, Yasuhiro; Sekine, Toshikazu

doi:10.1109/iscas.2013.6572406

Cited by 10 publications

(9 citation statements)

References 9 publications

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“…On the other hand, the TDPL is supplied with constant 1.8V of V dd , and the input discharge, charge, evaluation signals' dynamic frequency are 1.25-50MHz as well. The previous work in [12] reported the pre-layout simulation with active power clock frequency range is 1.25-125MHz. However, the more accurate information provided in this optimization work shown that the maximum speed of our proposed CSSAL multiplier is 50MHz.…”

Section: A Simulation Conditionmentioning

confidence: 99%

“…In recent, few papers of secure adiabatic logic have been published which referred to this work, such as SAL [10], and SyAL [11]. The SAL and SyAL have achieved low power and high resistance to DPA attacks as stated, however, the throughout evaluation in our previous work [12] found out that they still perform certain different current values for every input transition.…”

Section: Introductionmentioning

confidence: 98%

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Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Monteiro¹,

Takahashi²,

Sekine³

2013

IJMO

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Abstract-The bit-parallel multiplier over Galois filed arithmetic algorithm and the circuit architecture have been widely studied and implemented in cryptosystem. In this paper, we implement the proposed secure and low-power dual-rail adiabatic logic circuit into the bit-parallel cellular multiplier over GF(2 4 ). The full custom design of the layout has been designed in cadence virtuoso IC6.1 with the chip size of 172×155 m 2 , and the post-layout cyclical power consumption of 14pJ at 12.5MHz using 0.18μm CMOS technology has achieved; while, the well-known conventional TDPL logic in our work using the same technology occupied 183×m 2 of the chip size and 123pJ per cycle. The thoroughly investigation results define that our proposed logic improve energy reduction and the circuit immunity to side-channel attack in the low frequency application, whereas, the TDPL shows the better security performance at high frequency range.Index Terms-Bit-parallel multiplier, adiabatic, low-power, side channel attack, cryptography.

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Section: A Simulation Conditionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Monteiro¹,

Takahashi²,

Sekine³

2013

IJMO

Self Cite

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“…The logic design approaches such as Charge-Sharing Symmetric Adiabatic Logic (CSSAL) [4], Symmetric Adiabatic Logic (SyAL) [5], Secure Quasi-Adiabatic Logic (SQAL) [6], Symmetric Pass Gate Adiabatic Logic (SPGAL) [9] and Energy Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) [10] are the existing secure adiabatic logic approaches resilient to PAA.…”

Section: Introductionmentioning

confidence: 99%

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications

Raghav

Bartlett

Kale

2018

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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“…There are several energy efficient PAA resistant logic designs which are based on the adiabatic logic [10]- [17] such as Charge-Sharing Symmetric Adiabatic Logic (CSSAL) [10], Symmetric Adiabatic Logic (SyAL) [11], and Secure QuasiAdiabatic Logic (SQAL) [12]. All of these design styles make use of charge-sharing technique at the output/internal nodes and load balancing at the two output nodes to guarantee constant energy consumption.…”

Section: Introductionmentioning

confidence: 99%

“…Also, SPGAL [15], [16] and EE-SPFAL [17] are the recently proposed secure adiabatic logic designs, and have proven to be better than CSSAL [10], SyAL [10] and SQAL [10], a comparison of the performance between WCS-QuAL, SPGAL and EE-SPFAL on the basis of %NED and %NSD and energy dissipation is presented in this paper. To further evaluate and compare the performances, Galois Field, GF (2 4 ) bit-parallel multiplier was implemented and the impact of Process, Voltage, and Temperature (PVT) variations, power supply scaling and technology was investigated.…”

Section: Introductionmentioning

confidence: 99%

Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variations

Raghav

Bartlett

Kale

2017

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Abstract-In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of %NED and %NSD at all simulated frequencies. Also, all three 2-input gates using WCS-QuAL exhibits logic operation independent energy dissipation by dissipating nearly equal energy. Also, the energy dissipated by WCS-QuAL approaches to the energy dissipation of EE-SPFAL and SPGAL as the output load capacitance is increased above 100fF. To further evaluate and compare the performance GF (2 4 ) bit-parallel multiplier was implemented as a design example. The impact of PVT variations, power supply scaling and technology on the performance of the three logic designs was investigated and compared. Simulation results show that WCS-QuAL passed the functionality test against PVT variations and can perform well against the power supply scaling (from 1.8V to 0.5V). It also exhibits the least value of %NED and %NSD against PVT variations and when the power supply is scaled from 1.8V to 0.5V compared to EE-SPFAL and SPGAL. Also, the difference in energy dissipation between WCS-QuAL and EE-SPFAL decreases at tsmc 90nm technology.

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DPA resistance of charge-sharing symmetric adiabatic logic

Cited by 10 publications

References 9 publications

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications

Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variations

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