Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card

Abstract

Numerous articles and patents on the masking of logic gates in CMOS logic styles have been reported, however, less information is available with regards to comparing the single rail and dual-rail on masking input logic values. This paper investigates single-rail and dual-rail logic families that have been developed by the logic designers for secure logic implementations in cryptographic system. The novelty of this work is that we evaluate the dynamic logic and ditTerential logic for one-phase 2-inputs logic in adiabatic mode in SPICE simulation. We analyze the power consumption of logic circuit along 16 possible transitions of 2-inputs logic during one cycle. The power traces show that adiabatic ditTerentiai logic families are masking the input logic values, because they consume constant power during pre-charge and evaluation phases that enables the circuit to resist against power analysis attacks. Based on our results, we deduce that adiabatic ditTerentiailogic families are promising candidates for further development to obtain a far more robust secure logic for countermeasure against power analysis attacks in smart card. I. INT RODUCTIONPower analysis attacks have become a special threat for cryptanalysis algorithm designers, software developers and hardware engineers to maintain the security of secret key in cryptographic implementation, such as in smart card. During the past years, a lot of researches have been conducted on simple power analysis (SPA) and differential power analysis (DPA) [1,2] on mathematical algorithm level. The SPA is more focusing on the use of visual inspection techniques to identify relevant power fluctuations during cryptographic operations, hence it is vulnerable for attackers to identify the secret key by calculating the power consumption during cryptographic operations. DPA attacks are more advanced than SPA attacks in which they use the statical methods and digital processing techniques on large number of power consumption signals to reduce noise and strengthen the difference signals, so it will be obvious to distinguish between the logical zero and logical one. There was also an effort of Adi Shamir to protect smart card from two main attacks, such as DPA and SPA attacks by detaching two capacitors to smart card [3]. His work was to detach two capacitors to work as a power isolation element by switch control unit and four power transistors 978-1-4577-2166-3/111$26.00 ©2011 IEEE which are added to the smart card chip. To protect the secret keys during encryption and decryption execution of smart card from power analysis attackers, there are a lot of efforts to mask the secret keys on algorithm level and monitoring power consumption signals to withstand side channel attacks (SCA) of cryptographic systems [4]- [7].The fundamental issues of power analysis attacks on cryp tographic systems are closely related to electrical power consumption of hardware implementations. Regarding power consumption in cryptographic implementation such as smart card, logic design should be highly consider...

A novel power analysis attack resilient adiabatic logic without charge sharing

“…The proposed logic charge the same capacitance value for each input combination. Lastly, the existing logic designs have been assessed for their resistance against PAA using the inputs which do not follow the adiabatic principle [8]. Also the inputs used are the one which will not come out of an adiabatic circuit.…”

“…Fig. 2 (a) and (b) shows the 16 input transitions for 2-input gate as shown in [8] and the real life relevant adiabatic input transitions respectively. The problem with the input transitions of Fig 2(a) is that it favours the energy efficiency of the logic by removing the coupling effects and the NAL during the recovery phase of the power-clock.…”

“…On the other hand, there are several, energy efficient PAA resilient logic designs based on the adiabatic logic [7] such as Charge-Sharing Symmetric Adiabatic logic, CSSAL [8]. Symmetric Adiabatic Logic, SyAL [9], and Secure QuasiAdiabatic Logic, SQAL [10].…”

Low power adiabatic logic based on FinFETs

“…Ultra low-power adiabatic sequential circuits like D, JK, T flip-flops are explored in [7]. Besides, it was reported that the adiabatic logic styles have better differential power analysis (DPA) resistances than the conventional CMOS logic [8,9]. However, with the aggressive scaling of device technology and threshold voltage, the leakage current has increased significantly, becoming the main part of power consumption [10].…”

A partially-adiabatic energy-efficient logic family as a power analysis attack countermeasure

“…Almost no research exists in the security of adiabatic logic against power analysis attacks. A short analysis on a 2-input NAND gate was described in [6], but no conclusion was made regarding adiabatic logic's security based on the experiment. Additionally, no analysis on larger gates was done.…”