A partially-adiabatic energy-efficient logic family as a power analysis attack countermeasure

Cutitaru, Mihail; Belfore, Lee A.

doi:10.1109/acssc.2013.6810469

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…Authors in [8] and [9] introduce another family of adiabatic circuits that have better energy recovery comparing to other methods and uses single phase sine wave for the clock. The current spikes are reduced by a factor of 4 that makes the circuits attractive for power attach resistant and cryptography applications.…”

Section: Introductionmentioning

confidence: 99%

Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic

Hassanzadeh

Shabani

2015

JEEE

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In this paper low power implementation of parallel prefix adders using two phase adiabatic logic has been investigated. A new structure has been proposed for the main blocks of parallel prefix adder. Three parallel prefix adders including Kogge-Stone, Brent-Kung and Ripple Carry have been considered. The effects of power clock frequency and loading capacitance on the new blocks have also been considered. Simulation results using 180nm technology parameters and trapezoidal waveform show an average of 34% power reduction in the main building blocks of the adder at 200MHz clock frequency. This power reduces to 54% for sine wave power clock waveform. This research suggests adiabatic implementation of parallel prefix adders for low power microprocessor and signal processing applications.

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Section: Introductionmentioning

confidence: 99%

Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic

Hassanzadeh

Shabani

2015

JEEE

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Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications

Sanadhya¹,

Sharma²

2023

Springer Tracts in Electrical and Electronics Engineering

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Low Power ALU using Wave Shaping Diode Adiabatic Logic

Khindria¹,

Hingorani²,

Niranjan³

2022

IJVLSID

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The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

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A partially-adiabatic energy-efficient logic family as a power analysis attack countermeasure

Cited by 3 publications

References 5 publications

Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic

Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic

Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications

Low Power ALU using Wave Shaping Diode Adiabatic Logic

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