Low power adiabatic logic based on FinFETs

Liao, Nan; Cui, Xiaoxin; Liao, Kai; Ma, Kaisheng; Wu, Di; Wei, Wei; Li, Rui; Yu, Dunshan

doi:10.1007/s11432-013-4902-x

Cited by 26 publications

(11 citation statements)

References 24 publications

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“…4, achieves low power compared to other logics. It consists of two PMOS transistors and two NMOS transistors in cross coupled fashion [11][12][13][14]. The NMOS logic functional blocks are connected in parallel with the PMOS pull up transistors, forming a transmission gates.…”

Section: ) Positive Feedback Adiabatic Logic (Pfal)mentioning

confidence: 99%

“…The NMOS diode acts as an active load which provides high impedance path to the pck in order to control the discharging rate at the output nodes. The DC source incorporates the advantage of level-shifting technique to reduce leakage currents, provides faster switching and to achieve low power [11,13]. …”

Section: Proposed Enhanced Diode Connected DC Biased Positive Fementioning

confidence: 99%

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Enhanced Adiabatic Paradigm for Ultra Low Power and High-Speed Switching

Kumar¹

2018

IJRASET

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With the continuous rising expedition for miniaturization of VLSI technology, one of the key hubs of the research has been shifted in the direction of ultra low power paradigms. Over past few years, adiabatic paradigms have been premeditated and found to be effectual in realising LPVD's. This paper succinct some of the adiabatic logic families such as ECRL, PFAL and exploits an enhanced adiabatic logic know as Enhanced Diode Connected DC Biased Positive Feedback Adiabatic Logic (EDCDB-PFAL). A few useful constructs, such as Boolean logic gates and binary full adder are successfully modelled and verified by using proposed technique. The flexibility and simplicity of modelling, simulation and verification show the usefulness and applicability of EDCDB-PFAL for low power paradigms. This paper aims at evaluating the efficacy of proposed adiabatic logic circuit, in terms of power, delay and leakage current over conventional logic families and are examined using Tanner EDA Tool with 250nm technology. Keywords: Low power, Adiabatic switching, ECRL, PFAL, EDCDB-PFAL. I.INTRODUCTION Due to the advancements in VLSI technology over the years, transistors size has reached to minuscule size that concerns the designers with the increasing power dissipation [1]. The most significant types of power dissipation are Static and Dynamic power dissipation. The static power dissipation is due to internal leakages in a device during off state, whilst dynamic power dissipation is due to energy loss during charging and discharging of the output node capacitance of a transistor when keying takes place. To achieve low power various paradigms has been implemented over conventional logic such as sub threshold logic, multi threshold logic and adiabatic logic [2,3]. Adiabatic logic has been widely used as a low -power tool. The word adiabatic comes from thermodynamics that depicts a method where no energy acquaintances with the milieu and hence no dissipation of energy loss takes place. In the recent years, several adiabatic or energy recovery logic (ERL) paradigms have been exploited and have attained significant power savings compared to conventional circuits [1,[3][4][5]. Due to keying of circuits with output voltage swing causes energy transfer from power supply to the output node and to the ground causing more energy transfer in CMOS conventional techniques. Thus to increase the energy efficiency of the circuits and to achieve low power, adiabatic logic families are used that offers reduced power dissipation, recycling the energy drawn from the supply(V DD ), fast switching speed and less noise. In adiabatic paradigms, the charge flows back to the V DD rather than flowing from the output node capacitance of a transistor to the ground making it to reuse achieving low power [4,5]. This paper delineates as follows: section 2 presents the overview of convention logic and explicates briefly about the adiabatic design methodology. Section 3 elucidates briefly about the proposed Enhanced Diode Connected DC Biased Positive Feedback Adi...

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Section: ) Positive Feedback Adiabatic Logic (Pfal)mentioning

confidence: 99%

Section: Proposed Enhanced Diode Connected DC Biased Positive Fementioning

confidence: 99%

Enhanced Adiabatic Paradigm for Ultra Low Power and High-Speed Switching

Kumar¹

2018

IJRASET

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“…Though we have seen that Adiabatic logic is one of the options to reduce the switching power dissipation but still problem of leakage power dissipation is not addressed in MOSFET based adiabatic logic. Recently in [8] and [12] FinFET devices are used in different modes for building Adiabatic circuits and significant reduction in power dissipation because of reduced leakage current is achieved. In [9] Hisamoto et al proposed the FinFET structure (Double-gate MOSFET).…”

Section: Finfet (Double-gate) Adiabatic Circuitsmentioning

confidence: 99%

“…After that a number of papers like [7] have been published on power gating in MOSFET based adiabatic circuits. Recently Kai Liao et al in [8] and Nan Liao et al in [12] designed FinFET based adiabatic circuits and showed that FinFET based adiabatic circuit are more power efficient than their bulk MOSFET counterpart.…”

Section: Introductionmentioning

confidence: 99%

Power gating in FinFET Adiabatic circuits

Deo

Kima

Murugan³

2014

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)

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In this paper, we have implemented power gating in FinFET based Adiabatic circuits. Power gating is a low power design technique used in circuits having standby/sleep mode. Again adiabatic logic has very low switching power dissipation than compared to CMOS logic, also when FinFET devices are used in place of MOSFET then power dissipation can be further reduced. So we have used the combination of all these techniques to design low power digital circuits. For validating our idea we designed two power gated adiabatic circuits, first one is IPFAL Inverter and the second one is IPFAL 2:1 Multiplexer using PTM 45nm technology node for bulk MOSFET as well as FinFET.

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“…Because of the excellent control over short-channel effects and high current drive capability, novel multi-gate MOS devices have been regarded for years as the most attractive devices to continue the CMOS technology development following "Moore's law" [2]. Among which FinFET, mainly proposed by Hisamoto et al [3], has attracted considerable scholarly attention [4][5][6][7] and has been adopted as the basic device of VLSI by industry. Figure 1 shows the schematic view comparison between classical planar bulk n-channel MOSFET and that of FinFET.…”

mentioning

confidence: 99%

Recent research development of FinFETs

Xie

2016

Sci. China Phys. Mech. Astron.

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Low power adiabatic logic based on FinFETs

Cited by 26 publications

References 24 publications

Enhanced Adiabatic Paradigm for Ultra Low Power and High-Speed Switching

Enhanced Adiabatic Paradigm for Ultra Low Power and High-Speed Switching

Power gating in FinFET Adiabatic circuits

Recent research development of FinFETs

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