Power gating in FinFET Adiabatic circuits

Abstract

In this paper, we have implemented power gating in FinFET based Adiabatic circuits. Power gating is a low power design technique used in circuits having standby/sleep mode. Again adiabatic logic has very low switching power dissipation than compared to CMOS logic, also when FinFET devices are used in place of MOSFET then power dissipation can be further reduced. So we have used the combination of all these techniques to design low power digital circuits. For validating our idea we designed two power gated adiabatic circuits, first one is IPFAL Inverter and the second one is IPFAL 2:1 Multiplexer using PTM 45nm technology node for bulk MOSFET as well as FinFET.