The Band Pass Filters are commonly used in wireless receivers and transmitter. The usage of spiral inductor in the band pass filters requires large chip area which can increase the band pass filter size and is difficult to obtain high Qfactor. This paper presents the active inductor based band pass filter using TSMC 0.18μm RF CMOS process. The band pass filter is realized using active inductor with suitable input and output buffer stages. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator. This structure provides the negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The tuning of the center frequency is achieved through the controllable current sources. This active inductor demonstrates a maximum quality factor of 244 with a 154nH inductance. The simulation result of band pass filter designed at 100MHz has the gain of 6.129 dB and input return loss of -11.474 dB. The simulated IIP3 is -19 dBm and power consumed by the BPF is 28mW.

This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed. The conventional 6T TFET SRAM cell is designed using DG TFET of 30 nm. For the circuit simulation, the symbol of DG TFET is developed with the help of a look-up table based Verilog-A code. The radiation induced single event upset (SEU) causes a change in the stored data of SRAM cell. In order to improve the SEU sensitivity, the radiation hardening-by-design technique (RHBD) is introduced in 6T TFET SRAM cell by connecting the RC feedback loop between the two cross coupled inverters. The standby power of the TFET SRAM cell is calculated and compared before and after the radiation mitigation technique insertion.

This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 10 3 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 10 3 times and less propagation delay than that of hetero-junction NOR logic circuit.The structure of TFET consists of a p-i-n junction (ptype, intrinsic, n-type), in which the tunneling of electrons B. Lokesh

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