Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

Pown, M.; Lakshmi, B.

doi:10.1109/jeds.2020.3002265

Cited by 15 publications

(9 citation statements)

References 33 publications

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“…The pre-charge circuit gives high voltage to both the BL = '1' and BLB = '1' during the read operation. There is no BL voltage discharge if the proposed cell has a high value [19][20].…”

Section: T Rhbd Sram Cellmentioning

confidence: 99%

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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One of the most critical functions of a computer is memory, as it would be impossible for it to function e ciently without it. The main memory of a computer is known as Random Access Memory (RAM). It stores operating system software, applications, and other data for the central processor unit (CPU) to perform operations swiftly and e ciently. Unfortunately, traditional static RAM (SRAMs) in aerospace applications suffers from high soft error issues such as Single Event Upset (SEU). To overcome the soft error problems, many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD) have been developed, such as 12T We-Quatro, twelve-transistor (12T) Dice SRAM cells, and so on. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 x 32 array architecture. The power consumption of a 32 x 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 x 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology le is used to simulate the comparative analysis for the SRAM cell.

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“…The pre-charge circuit gives high voltage to both the BL = '1' and BLB = '1' during the read operation. There is no BL voltage discharge if the proposed cell has a high value [19][20].…”

Section: T Rhbd Sram Cellmentioning

confidence: 99%

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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“…But in SG‐FinFET, delay occurs in both read write operation. Hence, leakage control transistor is used for the minimization of leakage power and delay 17,18 …”

Section: Introductionmentioning

confidence: 99%

“…Hence, leakage control transistor is used for the minimization of leakage power and delay. 17,18 The design as well as execution of SGFinFETs based Power Efficient SRAM Cell utilizing the LECTOR (Low-Energy Concurrent Error Detection) Technique presents a notable emphasis on power efficiency, deliberately side lining the potential impacts on read and write speeds-both of which are traditionally considered as critical factors for overall SRAM performance. By adopting this approach, the researchers aim to address the growing importance of power consumption in modern electronic devices, particularly in battery-operated systems where energy efficiency is paramount.…”

mentioning

confidence: 99%

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

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Static random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

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“…The GaSb-InAs combination has been used for the hetero-junction TFET which gives non-overlapping bandgap. The effective bandgap for tunneling can be decreased even further by using this heterostructure [18]- [20]. To reduce the tunneling barrier, GaSb and InAs were chosen for the source and channel/drain respectively.…”

Section: Introductionmentioning

confidence: 99%

Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic

Boggarapu

Pown

et al. 2022

International Journal of Electronics

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This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 10 3 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 10 3 times and less propagation delay than that of hetero-junction NOR logic circuit.The structure of TFET consists of a p-i-n junction (ptype, intrinsic, n-type), in which the tunneling of electrons B. Lokesh

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Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

Cited by 15 publications

References 33 publications

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic

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