Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level

Monteiro, Câncio; Takahashi, Yasuhiro; Sekine, Toshikazu

doi:10.1016/j.mejo.2013.04.003

Cited by 46 publications

(25 citation statements)

References 25 publications

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“…Gate level countermeasures typically rely on new or adjusted logic families with balanced power consumption. Examples of PAA resistant logic families are Sense Amplifier Based Logic (SABL) [21], Wave Dynamic Differential Logic (WDDL) [12], dual-rail circuits [22], three phase logic [23], and adiabatic based logic styles meant to help reduce the incurred energy consumption overheads [24]. Similar to hardware countermeasures at the system level, these altered logic styles offer improved security at the expense of increased area and power consumption.…”

Section: A Prior Researchmentioning

confidence: 99%

Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure

Mayhew

Mureşan

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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In this paper we develop a general model based on the width of a decoupling NMOS gate capacitor for use in the design of decoupling based Power Analysis Attack (PAA) countermeasures. A polynomial equation was determined based on experimental data to link the width of the decoupling element with the data security provided by the countermeasure architecture. The proposed model is meant to act as a tool for a designer when considering the incurred design overheads when allocating area during the initial planning phase. Experimental data was collected from the simulation of a partial decoupling countermeasure test bench implemented in 65 nm TSMC technology with Correlation Power Analysis (CPA) attacks performed on traces collected at the power supply pin.

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Section: A Prior Researchmentioning

confidence: 99%

Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure

Mayhew

Mureşan

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…Previously proposed CSSAL inverter logic in the reference [5] is again described in Fig. 2(c) for secure logic evaluation and comparison.…”

Section: Analysis Of the Proposed Logicmentioning

confidence: 99%

“…In this work, the authors conduct further investigation of previously proposed charge-sharing symmetric adiabatic logic (CSSAL) [5] to verify the circuit stability in consuming uniform transitional energy dissipation in presence of CMOS threshold voltage variations. Few papers on an adiabatic logic have been published which referred to this work, such as 2N-2N2P [6], and symmetric adiabatic logic (SyAL) [7].…”

Section: Introductionmentioning

confidence: 99%

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Monteiro

Takahashi

Sekine

2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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This paper investigates the effectiveness of secure dual-rail adiabatic logic against power analysis attack under CMOS process variations. The ability of the previously proposed logic in multiplier over GF (2 4 ) is investigated in terms of transitional energy dissipation using 100 data samples from Monte Carlo simulation. The adiabatic multiplier circuits are simulated using 0.18-μm and 90-nm CMOS process at an operating power clock frequency of 12.5MHz. The SPICE simulation results show that the proposed CSSAL multiplier has high stability and strong immunity in consuming constant power than other investigated logic styles.

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“…The proposed charge-sharing symmetric adiabatic logic (CSSAL) operation was described in detail in [8]. We recall the CSSAL inverter logic in this paper for better understanding of the secure logic comparison with Fig.…”

Section: B Charge-sharing Symmetric Adiabatic Logicmentioning

confidence: 99%

“…In this work, our previously proposed CSSAL [8] is implemented in an 8-bit S-box circuit using the PPRM representation [5] for low peak current transition and low energy consumption by exploiting an adiabatic switch principle [9]. We have also implemented several dual-rail adiabatic logic styles, such as SyAL [10], 2N-2N2P [11], and Morioka's circuit [5] in the same S-box circuit and compared the results.…”

Section: Introductionmentioning

confidence: 99%

Process variation verification of low-power secure CSSAL AES S-box circuit

Monteiro

Takahashi

Sekine

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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In this work, we implement our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit using a multi-stage positive polarity Reed-Muller (PPRM) representation with a composite field technique. We evaluate the effectiveness of the CSSAL S-box circuit against side-channel attacks towards the variations of the CMOS process technology. The results of this paper are obtained from the SPICE simulation with 0.18-µm and 90-nm standard CMOS technology at an operating frequency band of 125 KHz-70 MHz.

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Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level

Cited by 46 publications

References 25 publications

Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure

Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Process variation verification of low-power secure CSSAL AES S-box circuit

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