A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

Osaki, Yuji; Hirose, Takahisa; Kuroki, Nobutaka; Numa, Masahiro

doi:10.1109/jssc.2012.2191320

Cited by 102 publications

(65 citation statements)

References 10 publications

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“…Average normalized EDP of TSCWLS (with respect to WLS) is only 69%. Table 1 shows the results of the proposed design and comparison with other previously proposed designs from [6][7][8][9][10]13]. From the comparison, it can be seen that the proposed design exhibits best performance and [9].…”

Section: Post-layout Resultsmentioning

confidence: 99%

“…Modified Wilson current-mirror based designs have also been proposed which only marginally improve the delay and the power dissipation [11,12]. Osaki et al used the current generators (CGs) which turn ON only when the input and output logic level differs [13]. Contention problem of [13] is discussed in [14], where they proposed a new design based on CGs and solved the problem through output feedback.…”

Section: Introductionmentioning

confidence: 99%

“…Osaki et al used the current generators (CGs) which turn ON only when the input and output logic level differs [13]. Contention problem of [13] is discussed in [14], where they proposed a new design based on CGs and solved the problem through output feedback. Their design uses 14 transistors, and proper sizing is required to charge the internal nodes and reduce the power dissipations of the inverter (output of which is fed back to the CGs).…”

Section: Introductionmentioning

confidence: 99%

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A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

2017

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Multiple voltage domains are commonplace in modern SoCs and level shifter (LS) circuits allow different voltage domains to be interfaced with each other. As the reduced supply voltages are extensively used in digital blocks for low-power operation, the conversion of sub-threshold voltage levels to full VDD signal becomes a particular problem. In this paper we present a new LS structure for the fast and energy-efficient conversion of extremely low voltage levels. The proposed LS is a two-stage structure consisting of a controlled Wilson current mirror and eliminates the negative feedback mechanism. Inverted output of the second stage controls the current through the first stage. If the input signal is logical high (VDDL) then the circuit will produce high output (VDDH) and the first stage is prepared to conduct the current for logical 0 input (0V). This improves the slew rate problem and enables fast and energy-efficient operation. Considering process corners at a 90-nm technology node, the proposed design reliably converts 150-mV input signal into 1 V output signal. Post-layout results show that the proposed LS exhibits a propagation delay of 16 ns, a total energy per transition of only 79 fJ, and a static power dissipation of 16.6 nW for a 200 mV input signal at 1-MHz, while loading 100 fF of capacitive load. ARTICLE HISTORY

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Section: Post-layout Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

2017

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“…Multi Threshold CMOS (MTCMOS) technique is used in the architecture of level shifter circuit. These circuit which gives robust voltage shifting from the deep sub-threshold to the above-threshold domain, while demonstrating fast response and low energy consumption [13]- [15].…”

Section: Related Workmentioning

confidence: 99%

Design of Low Power Level Shifter Circuit with Sleep Transistor Using MultiSupply Voltage Scheme

Prasath¹,

Kumar²

2016

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New low-power Level Shifter (LS) circuit is designed by using sleep transistor with Multi Threshold CMOS (MTCMOS) technique for robust logic voltage shifting from sub-threshold to abovethreshold domain. MultiSupply Voltage Design (MSVD) technique is mainly used for energy and speed in modern system-on-chip. In MSVD, level shifters are required to allow different voltage supply to shift from the lower power supply voltage to the higher power supply voltage. This new low-power level shifter circuit is also used for fast response and low leakage power consumption. This low leakage power consumption can be achieved through insertion of sleep transistor and proper transistors sizing. The proposed design efficiently converts 100 mv input signal into 1 v output signal and achieves the power of 2.56 nW by using 90 nm technology.

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“…Sub threshold leakage power increase exponentially as threshold voltage decreases. Stack method, Forced NMOS, Forced PMOS and sleepy keeper method are the some of the leakage current reduction methods [2]. When technology feature size scales down, supply voltage and threshold voltage also scale down.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Voltage Modified Wilson Current Mirror Circuits Based Energy Efficient Level Shifters

2017

IJAERD

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A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

Cited by 102 publications

References 10 publications

A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

Design of Low Power Level Shifter Circuit with Sleep Transistor Using MultiSupply Voltage Scheme

Design of Low Voltage Modified Wilson Current Mirror Circuits Based Energy Efficient Level Shifters

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