A low-power low-noise CMOS bio-potential amplifier for multi-channel neural recording with active DC-rejection and current sharing

Jomehei, Maryam Gharaei; Sheikhaei, Samad

doi:10.1016/j.mejo.2018.11.021

Cited by 18 publications

(5 citation statements)

References 31 publications

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“…N EXT generation of Brain Machine Interfaces (BMIs) enable an accurate and precise recording of neural signals to treat neurological disorders as well as to advance neuroscience research [1]- [6]. Neural recording interfaces with an escalated spatio-temporal resolution is thus highly desired in comprehending various neural interactions such as thoughts, cognition, perception, and actions as well as in recovering neurological diseases such as stroke [7], Parkinson's disease [8], [9], Epilepsy [10], [11], Alzheimer's disease [11], Schizophrenia [12], etc. [13].…”

Section: Introductionmentioning

confidence: 99%

“…An efficacious neural recording system requires to meet the requirements of miniaturized area, minimum tissue damage (low power dissipation), high channel count, noise performance, wireless transmission, and system power consumption [8], [26]- [28]. A trade-off between the key requirements including the power and noise performances of the analog front-end is very critical in designing the neural signal recording system.…”

Section: Introductionmentioning

confidence: 99%

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A Fully Integrated 1.13 NEF 32-Channel Neural Recording SoC With 12.5 pJ/Pulse IR-UWB Wireless Transmission for Brain Machine Interfaces

Tasneem,

Biswas,

Reza

et al. 2023

IEEE Access

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Monitoring electrical activity from numerous neurons with the help of a high-channel count neural recording system is crucial for the state-of-the-art approaches in neuroscience research and clinical treatment. The performance trade-offs such as channel count, total power consumption, noise, area, and robustness need to be optimized for compatibility in neural signal acquisition system. This work proposes an implantable 32-channel neural signal acquisition system-on-chip (SoC), which includes 32 neural amplifiers, an analog multiplexer (MUX), an analog-to-digital converter (ADC), and an impulse radio ultra-wide band (IR-UWB) transmitter designed using 180 nm CMOS process. The neural amplifier allows to detect local field potentials (LFP) and action potentials (AP) separately in a programmable gainbandwidth setup. It achieves 48 dB gain within the 0.2-345 Hz for LFPs and a gain of 59.7 dB within the 310-20.7 kHz frequency range for APs. A 10 bit SAR-ADC is designed with reconfigurable sampling rate of 10-40 kSps achieving an FOM (Figure-of-Merit) of 629 fJ/step. The designed IR-UWB transmitter can transmit data at 100 Mbps data rate with an energy efficiency of 12.5 pJ/pulse. The proposed system shows a promising reconfigurable multi-channel neural signal recording paradigm for neuroscience research and Brain Machine Interfaces (BMIs) applications. INDEX TERMS Multi-channel neural amplifier, SAR-ADC, reconfigurability, IR-UWB transmitter.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Fully Integrated 1.13 NEF 32-Channel Neural Recording SoC With 12.5 pJ/Pulse IR-UWB Wireless Transmission for Brain Machine Interfaces

Tasneem,

Biswas,

Reza

et al. 2023

IEEE Access

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“…For the prolonged treatment of chronic diseases, a neural amplifier must fulfil several essential requirements. These encompass 1) a substantial input impedance, 2) minimal power usage to prevent tissue harm and optimize battery life [7], [8], [9], [10], 3) compact area for system miniaturization, 4) low-level of input-referred noise for accurate spike detection amidst background noise, 5) substantial common-mode rejection ratio, 6) elimination of DC voltage [11]. Furthermore, the need for electrode arrays with Fig.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power Low-Noise Biopotential Amplifier in 28 nm CMOS

Koleibi

Benhouria

Koua

et al. 2022

2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)

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This paper presents a compact low-power, lownoise bioamplifier for multi-channel electrode arrays, aimed at recording action potentials. The design we put forth attains a notable decrease in both size and power consumption. This is achieved by incorporating an active lowpass filter that doesn't rely on bulky DC-blocking capacitors, and by utilizing the TSMC 28 nm HPC CMOS technology. This paper presents extensive simulation results of noise and results from measured performance. With a mid-band gain of 58 dB, a -3 dB bandwidth of 7 kHz (from 150 Hz to 7.1 kHz), and an input-referred noise of 15.8 µV rms corresponding to a NEF of 12. The implemented design achieves a favourable tradeoff between noise, area, and power consumption, surpassing previous findings in terms of size and power. The amplifier occupies the smallest area of 2500 µm 2 and consumes only 3.4 µW from a 1.2 V power supply corresponding to a power efficiency factor of 175 and an area efficiency factor of 0.43, respectively.

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“…On the other hand, there is an alternative method that blocks these DC offset voltages by using a low-pass filter in the feedback path, which is called DC-coupled input offset rejection. The authors in Enz et al (1995), Yazicioglu et al (2008), Muller et al (2012), Biederman et al (2013), Lee et al (2019), Jomehei and Sheikhaei (2019), Cabrera et al (2020), and Farouk et al (2020) use this method, however, it requires a huge capacitor or high power consumption amplifier in the feedback path.…”

Section: Introductionmentioning

confidence: 99%

Low-Cutoff Frequency Reduction in Neural Amplifiers: Analysis and Implementation in CMOS 65 nm

2021

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Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoff frequency due to the short-channel effects. To improve the low-cutoff frequency, one solution is to increase the feedback capacitors' value. This solution is not desirable, as the input capacitors have to be increased to maintain the same gain, which increases the area and decreases the input impedance of the neural amplifier. We analytically analyze the small-signal behavior of the neural amplifier and prove that the main reason for the increase of the low-cutoff frequency in advanced CMOS technologies is the reduction of the input resistance of the operational transconductance amplifier (OTA). We also show that the reduction of the input resistance of the OTA is due to the increase in the gate oxide leakage in the input transistors. In this paper, we explore this fact and propose two solutions to reduce the low-cutoff frequency without increasing the value of the feedback capacitor. The first solution is performed by only simulation and is called cross-coupled positive feedback that uses pseudoresistors to provide a negative resistance to increase the input resistance of the OTA. As an advantage, only standard CMOS transistors are used in this method. Simulation results show that a low-cutoff frequency of 1.5 Hz is achieved while the midband gain is 30.4 dB at 1 V. In addition, the power consumption is 0.6 μW. In the second method, we utilize thick-oxide MOS transistors in the input differential pair of the OTA. We designed and fabricated the second method in the 65 nm TSMC CMOS process. Measured results are obtained by in vitro recordings on slices of mouse brainstem. The measurement results show that the bandwidth is between 2 Hz and 5.6 kHz. The neural amplifier has 34.3 dB voltage gain in midband and consumes 3.63 μW at 1 V power supply. The measurement results show an input-referred noise of 6.1 μVrms and occupy 0.04 mm2 silicon area.

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A low-power low-noise CMOS bio-potential amplifier for multi-channel neural recording with active DC-rejection and current sharing

Cited by 18 publications

References 31 publications

A Fully Integrated 1.13 NEF 32-Channel Neural Recording SoC With 12.5 pJ/Pulse IR-UWB Wireless Transmission for Brain Machine Interfaces

A Fully Integrated 1.13 NEF 32-Channel Neural Recording SoC With 12.5 pJ/Pulse IR-UWB Wireless Transmission for Brain Machine Interfaces

A Low-Power Low-Noise Biopotential Amplifier in 28 nm CMOS

Low-Cutoff Frequency Reduction in Neural Amplifiers: Analysis and Implementation in CMOS 65 nm

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