A low-power low-offset dynamic comparator for analog to digital converters

Hassanpourghadi, Mohsen; Zamani, Mohsen; Sharifkhani, Mohammad

doi:10.1016/j.mejo.2013.11.012

Cited by 66 publications

(12 citation statements)

References 17 publications

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“…The dynamic comparator in [12] has a higher maximum operating frequency of 2.5 GHz (from simulation results), but its energy consumption is approximately 5× higher than that of our proposed comparator. The comparator in [17] has lower energy consumption (from the simulation results) but suffers from a lower speed and a larger offset voltage.…”

Section: A Simulation Resultsmentioning

confidence: 99%

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

et al. 2019

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Low-power, high-speed dynamic comparators are highly desirable in the design of highspeed analog-to-digital converters (ADC) and digital I/O circuits. Most dynamic comparators use a pair of cross-coupled inverters as the latching stage, which provides strong positive feedback, to accelerate the comparison and reduce the static power consumption. The delay of the comparator is mainly determined by the total effective transconductance of the latching stage. The delay not only limits the maximum operating frequency but also extends the period of the metastable state of the latching stage; hence, it increases energy consumption. However, at the beginning of the comparison phase, the conventional latching stage has two transistors with zero gate-to-source voltage, which degrade the total effective transconductance of the latching stage. In this paper, a novel low-power, high-speed dynamic comparator with a new latching stage is presented. The proposed latching stage uses separated gate-biasing cross-coupled transistors instead of the conventional cross-coupled inverter structure. The simple proposed latching stage improves its effective total transconductance at the beginning of the comparison phase, which leads to a much faster comparison and lowers energy consumption. The comparator is analyzed and compared to its prior type in terms of delay and power consumption via simulations and measurements. The experimental results demonstrate that the proposed comparator operates from a 1.2-V supply and consumes 110-fJ energy per comparison, with sampling speeds up to 2 GS/s.

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Section: A Simulation Resultsmentioning

confidence: 99%

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

et al. 2019

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“…As mentioned in the previous section, the major challenge in flash ADCs is the comparators and reference voltages of them causing the greatest impact power consumption, area occupation on a chip and limited speed, the second problem is the encoders' delay. Above-mentioned setbacks are conducted in a number of papers [10][11][12][13][14][15][16][17][18][19][20]. In this paper, both the above-mentioned problems are covered and a new flash ADC is presented.…”

Section: Review Of the Structure Flash Adcmentioning

confidence: 99%

“…Comparators and reference voltage are the most important parts of the flash converter .In order to minimise the power consumption and optimise the comparator circuit many research works have been conducted in this field and different types of comparators have been designed [10][11][12][13][14]. However, comparators need reference voltages and it is difficult to produce multiple reference voltages in flash converter.…”

Section: Introductionmentioning

confidence: 99%

Approach for low power high speed 4‐bit flash analogue to digital converter

Razavi

Tavakoli

Setoudeh

2020

IET Circuits, Devices & Systems

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In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.

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“…The output of this differential pair is taken from the output node which incorporates folded cascode current mirrors as source and sink. M4, M5, M6, and M7 form a current source while, on the other hand, M8, M9, M10, and M11 forms a current sink [26]. The sensing circuit comprises Ms1 and Ms2, which sense the common mode signal from the output node.…”

Section: Circuit Descriptionmentioning

confidence: 99%

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Khatak

Kumar

Dhull

2018

JLPEA

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A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

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A low-power low-offset dynamic comparator for analog to digital converters

Cited by 66 publications

References 17 publications

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

Approach for low power high speed 4‐bit flash analogue to digital converter

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

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