A Low-power Motion Compensation IP Core Design for MPEG-1/2/4 Video Decoding

Chien, Charles; Chen, Ho-Chun; Huang, Lin-Chieh; Guo, Jiun-In

doi:10.1109/iscas.2005.1465642

Cited by 6 publications

(1 citation statement)

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“…Several parts of the MPEG-1 video decoder have been designed for low power consumption, which is of great importance in the realisation of portable multimedia applications. For example, [3] describes a motion compensation IP core for the MPEG-1 video decoding that reduces the power consumption during the pixel interpolation. In [2], a variable length decoder IP core for the MPEG-1 video decoding that reduces power consumption by applying a partial combinational component enabling technique is presented.…”

Section: Introductionmentioning

confidence: 99%

Design of a low power MPEG-1 motion vector reconstructor

Ochoa-Montiel

Al-Hashimi

Kollig³

2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

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This paper describes the design of a low power MPEG-1 motion vector reconstructor using behavioural synthesis methodology. Various techniques, such as appropriate voltage scaling after clock and operations throughput selection, and reduction of multiplexer-based interconnection complexity are used to reduce power consumption. The design has been implemented based on a library components previously synthesised using Synplify ASIC w design has been performed through timing simulation with ModelSim, whereas power analysis is based on the reports obtained with PrimePower from Synopsys. The proposed design dissipates 42% less power than a power unaware design operated at the maximum supply voltage of the library components, i.e. 1.32V.

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Section: Introductionmentioning

confidence: 99%