1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) 1999
DOI: 10.1109/vlsic.1999.797223
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A low-power multi-gigabit CMOS/SIMOX LSI design using two power supply voltages

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Cited by 5 publications
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“…SOI devices have excellent RF performance even at voltages below 1V because of reduced capacitance in the drain region compared to bulk-CMOS technologies. Moreover, fully-depleted CMOS/SIMOX technology allows undoped MOSFETs with no process steps added to the normal digital CMOS/SIMOX LSI fabrication [1]. The undoped MOSFETs are normally-on transistors and can be made simply by masking in the channel-doping process.…”
mentioning
confidence: 99%
“…SOI devices have excellent RF performance even at voltages below 1V because of reduced capacitance in the drain region compared to bulk-CMOS technologies. Moreover, fully-depleted CMOS/SIMOX technology allows undoped MOSFETs with no process steps added to the normal digital CMOS/SIMOX LSI fabrication [1]. The undoped MOSFETs are normally-on transistors and can be made simply by masking in the channel-doping process.…”
mentioning
confidence: 99%