A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs

Shibata, Noriyoshi; Wantanabe, M.; Sato, Yasuhiro; Ishihara, Tatsuya; Komine, Yukio

doi:10.1109/4.953481

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A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs

Cited by 10 publications

References 27 publications

Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

DRG-cache: a data retention gated-ground cache for low power

A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell

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