A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell

Configurable digital transceiver for IEEE 802.15.4 networks

“…Differential addressing [8] is implemented to circumvent this behavior. Here, the current level until which the FIFO is filled is saved as a difference of two pointers instead of saving it as an absolute memory address.…”

A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design

“…All the cells are initialized to 0 before starting operation. (This can be done by a multi-cycle reset operation similar to the one in [4] or adding a global reset input to all the cells. )…”

“…A high-speed FIFO is usually implemented using a two-port RAM array (one port for read operation and the other for write operation) and two address pointers for tracing the read and write memory accesses [1,2,3,4]. An address pointer functions as a token-passing circuit which passes a logic 1 (the token) along its outputs, which control the word-line drivers or column selection circuits of the RAM array.…”

“…D flip-flops (DFFs) without clear inputs are used in address pointer design [4], which results in a 17% layout area saving. However, due to the lack of a global clear input, the address pointer must go through a length multi-cycle reset operation for initialization.…”

A Low-Power Delay Buffer Using Gated Driver Tree

“…Since the ring counter is made up of an array of D-type flip-flops (DFFs) triggered by a global clock signal and all except one DFFs have a value of "0," it is possible to disable the clock signal to most DFFs. Such a gated-clock ring counter is implemented in [6] to compose a low-power first-in-first-out (FIFO) memory.…”