This paper presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. Both simulation results and experimental results show great improvement in power consumption. A 256 8 delay buffer is fabricated and verified in 0.18 m CMOS technology and it dissipates only 2.56 mW when operating at 135 MHz from 1.8-V supply voltage.

In this paper, we have completed system and adopted is the VBLAST algorithm [1]. In particular this circuit design of a high-speed baseband transceiver for a paper will address the following topics: high-rate wireless LAN. This system adopts multi-input(1) architecture of the baseband transceiver multi-output (MIMO) orthogonal frequency division(2) construction of the baseband equivalent MIMO =multiplexing (OFDM) technique, which can be more channel model at 60GHz robust to channel effects in the band that the WLAN will (3) system simulation operate. Detail design of the baseband receiver is (4) circuit design completed and functional simulation shows promising results for the proposed baseband transceiver. Further circuit design indicates that the receiver can support a II. SYSTEMDESIGN signal bandwidth higher than 150MHz and channel bit A. Transmitter Architecture rate well above 1Gbps.The transmitter is divided into two blocks: frequency domain and time domain (see Fig. 1). The long preamble (LP) I. INTRODUCTION and short preamble (SP), together with random data bits, are WLAN has been very popular as the infrastructure for generated, convolutional code encoded, scrambled, and ubiquitous computing and communication. Current OFDMmapped to QAM constellation. Then the frequency domain based WLAN support up to 100 Mbps of data rate. MIMO data are split into two streams and sent to two transmitters, extension of the current standard promise a data rate up to one for each antenna. The data are passed on to the inverse hundreds of Mbps. 60-GHz signals enjoy (suffer) from that FFT blocks with bit-reverse processing. Finally, the resulting fact that penetration through concrete wall is impossible.waveforms are inserted with cyclic prefix and then Therefore, in this band not only wireless communication waveform-shaped. without eavesdropping can be established, but also higher data rate can be provided. B. MIMO Channel Model This paper delivers a design of a high-speed baseband We used the channel model coefficients listed in [2] to receiver that is aimed toward a 60-GHz WLAN using the construct an MIMO multi-path baseband model. The MIMO OFDM technique. The MIMO scheme that is sampling rate is set to 160 MHz. Four such channels are Frequency.V DomnairPiroesS-ieg Short Preamble Tithe Domhain P6roessing LPtype-4 Long Preamnbte m 7Sarnple-bas_ed ltttS Bits Scrambler rE -Insrion Wave Tx out SGeNeAto Mapper Output Buffer Sapn Fig. 1: Transmitter architecture -frequency-domain and time-domain processing.