DRG-cache: a data retention gated-ground cache for low power

Agarwal, A.; Li, Hai; Roy, K.

doi:10.1109/dac.2002.1012671

Cited by 74 publications

(81 citation statements)

References 10 publications

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“…The ground gated transistor is controlled by the external signal which is connected to the word-line. The leakage current significantly reduced through fundamentally "gating" the cell's power supply by "switch on" in the active mode and "switch off" in an idle mode [83]. …”

Section: Data Retention Gated-ground (Drg)mentioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

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Section: Data Retention Gated-ground (Drg)mentioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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“…The amount of gate leakage current has increased gradually and is probable to become analogous or even superior to the sub threshold leakage for future CMOS devices [15]. This has been proposed to decrease sub-threshold leakage in SRAM cells of the numerous techniques [16], [17], [18], apply a selfcontrollable switch (SVL) [19] in active mode which allows full supply voltage to be applied and decreased supply voltage appears to be proficient for reducing gate leakage currents as well.…”

Section: "Self Controllable Voltage Level Circuit" (Svl)mentioning

confidence: 99%

Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology

Pandey¹,

Akashe²

2014

IJCA

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Reduction of power dissipation is one of the most important challenges in VLSI circuit design. Due to scaling, sub threshold leakage current plays a dominant role in total power dissipation. This paper illustrates application of power saving SVL technique on 2:1 NAND MUX architecture. This application offers significant reduction in leakage power and leakage current viz-a-viz previous techniques. Self controllable Voltage Level Circuit (SVL) technique drastically reduces stand by leakage power and leakage current of CMOS logic circuits. This technique compare the optimization of leakage current and leakage power using two different design of 2:1 MUX. First is conventional MUX and other one is NAND based 2:1 MUX. The performance of this designed circuit is realized on a standard 45nm technology by using 0.7v supply voltage. It is easily concluded that this 2:1 nand based MUX achieves 651.9 Pw leakage power (Pst) and leakage current 1.020nA in standby mode, Where as conventional MUX achieved 2.04nA leakage current and 0.5nW leakage power.

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“…Sleepy Transistor [5], Sleepy Stack [6], DRG Cache [7], Gated V DD [8], Sleepy Keeper [9], Multiple Power Gating [10], VCLEARIT [11] are some of the circuit level techniques for low leak operation. Different multi V TH techniques for low leak operations discussed in literature are Dual threshold CMOS [12] Variable threshold CMOS (VTMOS) [13].…”

Section: (V Gs -V T )/ (Nv T ) [1-e (-V Ds / V T ) ]mentioning

confidence: 99%

Novel Low Power Logic Gates using Sleepy Techniques

Kalal¹,

I²,

Pawar³

2015

IJAREEIE

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ABSTRACT:The subthreshold voltage is declining in successive nanometre technologies and has an associated effect of enhanced leakage current. This causes the static (leakage) power to be a vital portion of total power dissipation in a VLSI circuit. Two novel circuit techniques for leakage current reduction in logic gates are presented in this work. The proposed circuit techniques are applied to universal NAND and NOR logic gates. The performance of these low leak gates is compared with earlier CMOS circuit leakage minimization techniques applied to these gates. The novel ultra low leak technique provides maximum leakage current reduction with lower output levels. Low Power State Retention-LPSR technique provides lower leakage power and the state of the gate can also be retained in sleep mode. The proposed low leak gates are designed and simulated using cadence design tools for 90 nm CMOS process technology. The leakage power for the novel methods during sleep mode is found to be better with and without state retention as compared to earlier best known techniques. The dynamic power dissipation for the proposed techniques is least. KEYWORDS:Leakage power, sleep transistor, power gating, total average power, state retention. I.INTRODUCTIONFor successive technology generations the transistor feature sizes are becoming smaller and the channel length is reducing. The threshold voltage and gate oxide thickness are also being scaled down [1] to maintain performance.The subthreshold voltage is going down to keep pace with reduced supply voltage for scaled down technologies in order to have good performance. The lower subthreshold voltage in nanometre technologies gives rise to enhanced leakage current because transistors cannot be switched off completely. Subthreshold current is the drain to source leakage current when the transistor is off. Leakage current acts as a limiting factor for further scaling down of transistors as per the International Roadmap for Semiconductor Technology (IRST) [2]. Thus it is essential to reduce leakage (static) power consumption during the idle or standby states of the circuits.When a CMOS circuit is active, the total power dissipation is due to dynamic and static components. In the inactive (standby) mode, the CMOS circuit dissipates power due to the standby leakage current [3] [4]. Sub-threshold leakage current for V GS < V T is given by2) In these equations I DSO is current at threshold dependent (on process and device geometry), V TO is the zero bias threshold voltage, γ -is the linearized body effect coefficient, η represents the effect of V DS on threshold voltage, n is the sub-threshold swing coefficient, V T is thermal voltage respectively. η term describes Drain Induced Barrier Lowering. Subthreshold conduction is enhanced by Drain Induced Barrier Lowering (DIBL) in which positive V DS effectively reduces V T . Leakage current doubles for every 8 0 to 10 0 K rise in temperature.The subthreshold leakage current can be reduced by increasing threshold voltage V TO , increasing source ...

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DRG-cache: a data retention gated-ground cache for low power

Cited by 74 publications

References 10 publications

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology

Novel Low Power Logic Gates using Sleepy Techniques

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