Abstract:ABSTRACT:The subthreshold voltage is declining in successive nanometre technologies and has an associated effect of enhanced leakage current. This causes the static (leakage) power to be a vital portion of total power dissipation in a VLSI circuit. Two novel circuit techniques for leakage current reduction in logic gates are presented in this work. The proposed circuit techniques are applied to universal NAND and NOR logic gates. The performance of these low leak gates is compared with earlier CMOS circuit lea… Show more
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