ABSTRACT:The subthreshold voltage is declining in successive nanometre technologies and has an associated effect of enhanced leakage current. This causes the static (leakage) power to be a vital portion of total power dissipation in a VLSI circuit. Two novel circuit techniques for leakage current reduction in logic gates are presented in this work. The proposed circuit techniques are applied to universal NAND and NOR logic gates. The performance of these low leak gates is compared with earlier CMOS circuit leakage minimization techniques applied to these gates. The novel ultra low leak technique provides maximum leakage current reduction with lower output levels. Low Power State Retention-LPSR technique provides lower leakage power and the state of the gate can also be retained in sleep mode. The proposed low leak gates are designed and simulated using cadence design tools for 90 nm CMOS process technology. The leakage power for the novel methods during sleep mode is found to be better with and without state retention as compared to earlier best known techniques. The dynamic power dissipation for the proposed techniques is least. KEYWORDS:Leakage power, sleep transistor, power gating, total average power, state retention. I.INTRODUCTIONFor successive technology generations the transistor feature sizes are becoming smaller and the channel length is reducing. The threshold voltage and gate oxide thickness are also being scaled down [1] to maintain performance.The subthreshold voltage is going down to keep pace with reduced supply voltage for scaled down technologies in order to have good performance. The lower subthreshold voltage in nanometre technologies gives rise to enhanced leakage current because transistors cannot be switched off completely. Subthreshold current is the drain to source leakage current when the transistor is off. Leakage current acts as a limiting factor for further scaling down of transistors as per the International Roadmap for Semiconductor Technology (IRST) [2]. Thus it is essential to reduce leakage (static) power consumption during the idle or standby states of the circuits.When a CMOS circuit is active, the total power dissipation is due to dynamic and static components. In the inactive (standby) mode, the CMOS circuit dissipates power due to the standby leakage current [3] [4]. Sub-threshold leakage current for V GS < V T is given by2) In these equations I DSO is current at threshold dependent (on process and device geometry), V TO is the zero bias threshold voltage, γ -is the linearized body effect coefficient, η represents the effect of V DS on threshold voltage, n is the sub-threshold swing coefficient, V T is thermal voltage respectively. η term describes Drain Induced Barrier Lowering. Subthreshold conduction is enhanced by Drain Induced Barrier Lowering (DIBL) in which positive V DS effectively reduces V T . Leakage current doubles for every 8 0 to 10 0 K rise in temperature.The subthreshold leakage current can be reduced by increasing threshold voltage V TO , increasing source ...