A low-power on-chip LDO with advanced reference buffer

In this work, the design of a 0.18μm CMOS dual loop capacitor-less low-dropout regulator (LDO) to achieve fast-transient response and good power supple rejection (PSR) is proposed for system-on-chip (SoC) power supply. The proposed LDO has a high slew-rate fast loop for enhancing transient response capability, and the high gain slow loop to improve PSR. Results show that the LDO consumes 100μA quiescent current, delivering a 50mA load current over a 30pF load. The maximum transient output-voltage variation is within 10% of the output voltage with recovery time of less than 81ns with a load step between 500μA and 50mA with 50ns edge times. The PSR is better than 50dB at 1MHz.

Section: Fast-transient Dual Loop Ldo With High Psrmentioning

confidence: 99%

A fast-transient dual loop LDO with high PSR

Fang,

Jin,

Liu

et al. 2024

“…However, lower IQ usually leads to poor load transient response. Recently, various techniques have been proposed to obtain fast transient response while consuming low quiescent current in LDO circuits [11,12,13,14,15,16,17,18,19].…”

Section: Introductionmentioning

confidence: 99%

Design of 300nA quiescent current and 300mA load capacity LDO with fast transient response

Yu,

Gao,

Zhang

et al. 2024

This paper presents a low dropout regulator (LDO) with a low quiescent current which helps to extend the standby time of battery-powered electronic devices. By utilizing the switchable bias technique in the error amplifier (EA), the bias current is switched to a higher level to accelerate the transient response under heavy load, while a low bias current is applied to EA to maintain a low quiescent current under light load. High speed current comparators and hysteresis control are combined to ensure fast and stable switching operation of the bias current. Moreover, an inrush current suppression circuit is proposed by recycling the switchable bias in EA. During startup, the bias current of EA can be kept low, and a reduced slew rate can be obtained at the pass gate voltage. The proposed LDO has been fabricated in 0.18-μm CMOS process, The experimental total quiescent current is 300nA under no-load condition. The maximum load current is 300mA. Measurement results show that the LDO can be settled within 8μs for a load current step of 0-50mA. In the startup process, the measured inrush current can be effectively limited.

“…For this purpose, The LDO regulators are commonly used for the stable operation and the power management of various mobile applications. As mobile devices continue to become smaller and more integrated, interest in capacitor-less LDO regulators is increasing [1,2,3,4,5,6,7]. In addition, the capacitor-less has the advantage of reducing the PCB board space, and must have a function to ensure the stability of the internal system for stable operation.…”

Section: Introductionmentioning

confidence: 99%

Design of capless LDO regulator with low voltage application based ESD protection circuit using SR-latch switch structure

Kwon

Koo

2022

The transient response characteristics such as overshoot and undershoot can be affected by the external capacitors of the LDO regulator. However, the capacitor-less LDO regulator proposed in this paper has an SR-Latch switch structure applied to the output terminal and gate terminal of the pass transistor in order to achieve improved transient response and secure excellent current driving capability. In addition, the proposed ESD protection device uses Penta-Well in low voltage applications embedded in the output stage and power line based on SCR (Silicon Control Rectifier) to provide improved ESD robustness characteristics. As a result, the transient response characteristics of the proposed LDO regulator with the SR-Latch switch structure were improved and the quiescent current was secured. The operating conditions of the proposed LDO regulator with the SR-Latch switch structure were set to an input voltage of 3.3V to 4.5V, maximum load current of 250mA, and an output voltage of 3V. As a result of the measurement, it was confirmed that the proposed LDO regulator maintained an undershoot voltage of 42 mV and an overshoot voltage of 31 mV when a load current of 250 mA was applied. In addition, HBM ESD robustness is guaranteed at 6kV.