A low power, programmable bias inverter quantizer (BIQ) flash ADC

Adimulam, Mahesh Kumar; Movva, Krishna Kumar; Kapoor, Amit; Srinivas, M.B.

doi:10.1109/vlsi-soc.2017.8203489

Cited by 2 publications

(4 citation statements)

References 18 publications

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“…In this approach, a set of additional devices (transistors or capacitors) is collectively connected to the critical nodes of a comparator through digitally controlled switches [1], [8]. Alternatively, a digitally controlled bias can be used to achieve similar effect without using redundant devices employing circuit degeneration [9], [10] or body biasing [11].…”

Section: Introductionmentioning

confidence: 99%

“…A CMOS inverter as a high-speed comparator is known in the literature as the Threshold Inverting Quantiser (TIQ) [12], Threshold Modified Comparator Circuit (TMCC) [13], and Bias Inverter Quantiser [9], and its applications have been explored for several decades [6], [8]. The schematic diagram of a TIQ circuit, example transfer characteristic, and basic formulas describing the circuit operation assuming the standard square-law MOS transistor model are shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…The main challenges, however, are the need for individual sizing (preprogramming) of the comparators, high sensitivity of the V GTH to process corners, mismatch, and supply voltage variation. Several methods for V GTH tuning other than the geometry scaling have been proposed employing circuit degeneration with resistors [10] or with transistors [9], as presented in Figs. 1b and c respectively, or using digitally controlled small-size switches, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, a fully autonomous trimming technique is proposed for the TIQ-based comparator through body biasing in Fully Depleted Silicon-on-Insulator (FDSOI) CMOS technology [14]. The proposed technique allows tuning V GTH with a single bias voltage, eliminating the need for circuit degeneration (thus, maximizing comparator speed), the use of switches (thus, minimizing the input capacitance), and the use of bias voltages within the core supply range ( [12], and V GTH tuning techniques employing, respectively, b) resistors [10], c) transistors [9], and d) switches [8].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing

Mroszczyk

Goodacre

Pavlidis

2019

IEEE Trans. Circuits Syst. II

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This paper presents the design of an energy efficient Flash analogue-to-digital converter (ADC) with Threshold Inverter Quantiser (TIQ) comparator employing advanced body biasing to compensate for the effects of parameter variability. The proposed calibration scheme is verified against process, voltage, and temperature (PVT) corners as well as random parameter variability (mismatch). Two proof-of-concept ADCs of 4-and 6bit precision are designed and verified in simulations in 28 nm Fully Depleted Silicon on Insulator (FDSOI) technology. The 6-bit converter achieves sampling rate of 3 GS/s, energy efficiency per conversion step below 20 fJ, and precision of 5.2 effective number of bits (ENOB). The proposed ADC architecture is dedicated to high-speed and low-precision applications, such as communication transceivers and data acquisition systems where area and energy efficiency are paramount. Index Terms-Flash analog-to-digital converter (ADC), offset calibration, threshold inverter quantiser (TIQ), body biasing. This paragraph of the first footnote will contain the date on which you submitted your brief for review. This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671578.

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