No abstract

This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down to 120 mV with single ended signaling. The compensation method has negligible impact on the circuit performance and silicon area, not typically achievable by device geometry scaling. The proof-ofconcept transceiver is implemented in a 65 nm CMOS technology and exhibits up to 4× higher energy efficiency at 1 Gb/s speed for 2.5 mm long chip-to-chip interconnect, as compared to state-of-the-art full swing communication schemes operating under the same conditions. The transceiver is suitable for parallel interfaces in 2.5-D integrated systems.

This paper presents the analysis and design of a tunable CMOS delay gate with improved matching properties as compared with the commonly used "current starved inverter" (CSI). The main difference between these structures lies in the location of the current limiting transistor on the inverter's output rather than on the side of the power rail. This improves the dynamic performance of the proposed "output split inverter" (OSI) circuit reducing the influence of the MOS transistor mismatch on the generated delay time variability. A test chip including two arrays consisting of 512 16-stage delay lines employing the CSI and OSI gates has been designed and fabricated in a standard 90 nm CMOS technology. The experimental results show that the proposed OSI circuit is about 10-50% more accurate than the conventional current starved inverter with no penalty in terms of the increased area, power consumption or complexity. Applications of the proposed circuit are in the design of time-to-digital converters (TDCs), delay locked loops, readout circuits for particle detection and time-based asynchronous computation systems.

Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication, AD conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to "traditional" geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the number and size of the switches, and the size of the inverter, using models from a 65 nm CMOS technology. The case study of a comparator circuit is further investigated in terms of the reliability, energy, and area, and compared against the geometry scaling approach.

No abstract