The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits

Mroszczyk, Przemyslaw; Dudek, Piotr

doi:10.1109/iscas.2014.6865450

Cited by 10 publications

(7 citation statements)

References 6 publications

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“…The separation of processing units and memories remains a fundamental principle of von Neumann architecture computers even though there are many efforts towards increasing parallelism [7]. In order to improve Bayesian inference efficiency, several different specific hardware or circuits have been proposed such as FPGA [8] and analog circuits [9]. Even though these works make an improvement on inference efficiency, there are still some shortcomings with the consideration of stochastic computing.…”

Section: Introductionmentioning

confidence: 99%

Analytical Macrospin Modeling of the Stochastic Switching Time of Spin-Transfer Torque Devices

Vincent

Locatelli

Klein

et al. 2015

IEEE Trans. Electron Devices

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Owing to their nonvolatility, outstanding endurance, high write and read speeds, and CMOS process compatibility, spin-transfer torque magnetoresistive memories (MRAMs) are prime candidates for innovative memory applications. However, the switching delay of their core components-the magnetic tunnel junctions (MTJs)-is a stochastic quantity. To account for this in electronic design, only partial models (working in extreme regimes) are available. In this paper, we propose an analytical model for the stochastic switching delay of a current-driven MTJ, with in-plane magnetization, that agrees with physical simulations, from low-to high-current regimes through intermediate regime. We performed physical macrospin simulations of MTJs for a wide range of current. We developed an analytical model for the mean switching delay that fits those simulations results, and smoothly connects well-accepted models for the extreme low and extreme high currents limits. In addition, a probability distribution in agreement with our simulations results is proposed, leading to a full model of the stochastic switching delay. An example for the application of the model is proposed. Our analytical model can help to evaluate the error rate in MRAM designs, and allow designing innovative electronic circuits that exploit the intrinsic stochastic behavior of MTJs as a beneficial feature.

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Section: Introductionmentioning

confidence: 99%

Analytical Macrospin Modeling of the Stochastic Switching Time of Spin-Transfer Torque Devices

Vincent

Locatelli

Klein

et al. 2015

IEEE Trans. Electron Devices

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“…However, it is difficult to leverage the parallelism of stochastic computing algorithms on traditional von-Neumann architectures [6]. Hence, reconfigurable approach [7] and analog computing [8] [9] is utilized to realize stochastic computing in order to improve the Bayesian inference efficiency. The stochastic computing are usually realized by bit-wise operations on stochastic bitstreams which is created by pseudo-random number generators (RNG) and comparators as shown in Fig.…”

mentioning

confidence: 99%

“…Sun's model, the equation conventionally used to describe the high-current regime, actually diverges in this intermediate current regime. For this reason, the current models usually ignore the intermediate regime [8]- [10], although it is, particularly, relevant for applications [16].…”

mentioning

confidence: 99%

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

Jia

Yang

Dai

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computingintensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this work, a spintronics based stochastic computing approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build stochastic bitstream generator (SBG) for stochastic computing with hybrid CMOS/MTJ circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and stochastic computing logic. A deviceto-architecture level framework is proposed to evaluate the performance of spintronics based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about 12× than MTJ-based approach with 45% design area overhead and about 26× than FPGA-based approach.

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“…Implementation of a Bayesian inference network on conventional general-purpose computers is inefficient in terms of area and energy consumption since a large number of complex floating point calculations need to be performed to compute the probability of occurrence of a particular variable since multiple causal variables are involved in the network. Hence, various approaches for BN hardware implementation have been proposed based on synthesizable hardware such as Field Programmable Gate Arrays 26,27 , fully digital system with stochastic digital circuit 28,29 , analog based probabilistic hardware for inference 30,31 , and mixed-signal approach (Muller C-Elements) 32 . However, multiple transistors are required to implement the functionality of a single stochastic element, thereby leading to an inefficient design.…”

Section: Bayesian Network Based On Stochastic Mtjmentioning

confidence: 99%

Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference

Shim¹,

Chen²,

Sengupta³

et al. 2017

Sci Rep

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Probabilistic inference from real-time input data is becoming increasingly popular and may be one of the potential pathways at enabling cognitive intelligence. As a matter of fact, preliminary research has revealed that stochastic functionalities also underlie the spiking behavior of neurons in cortical microcircuits of the human brain. In tune with such observations, neuromorphic and other unconventional computing platforms have recently started adopting the usage of computational units that generate outputs probabilistically, depending on the magnitude of the input stimulus. In this work, we experimentally demonstrate a spintronic device that offers a direct mapping to the functionality of such a controllable stochastic switching element. We show that the probabilistic switching of Ta/CoFeB/MgO heterostructures in presence of spin-orbit torque and thermal noise can be harnessed to enable probabilistic inference in a plethora of unconventional computing scenarios. This work can potentially pave the way for hardware that directly mimics the computational units of Bayesian inference.

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The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits

Cited by 10 publications

References 6 publications

Analytical Macrospin Modeling of the Stochastic Switching Time of Spin-Transfer Torque Devices

Analytical Macrospin Modeling of the Stochastic Switching Time of Spin-Transfer Torque Devices

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference

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