Mismatch Compensation Technique for Inverter-Based CMOS Circuits

Abstract

Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication, AD conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to "traditional" geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the number and size of the switches, and the size of the inverter, using models from a 65 nm CMOS technology. The case study of a comparator circuit is further investigated in terms of the reliability, energy, and area, and compared against the geometry scaling approach.

Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing

“…12, the statistical parameters of V GTH after compensation in terms of number of the trimming steps K, are illustrated assuming combined process and mismatch variability. Note that the effectiveness of trimming grows with K reaching σ VGTH ≈ 300 µV for K = 64 which already approaches the input referred noise level [8]. The V GTH after trimming for a constant reference and variable supply voltage V DD is shown in Fig.…”

“…Another approach to mitigate parameter variability is based on digitally controlled trimming. In this approach, a set of additional devices (transistors or capacitors) is collectively connected to the critical nodes of a comparator through digitally controlled switches [1], [8]. Alternatively, a digitally controlled bias can be used to achieve similar effect without using redundant devices employing circuit degeneration [9], [10] or body biasing [11].…”

“…A CMOS inverter as a high-speed comparator is known in the literature as the Threshold Inverting Quantiser (TIQ) [12], Threshold Modified Comparator Circuit (TMCC) [13], and Bias Inverter Quantiser [9], and its applications have been explored for several decades [6], [8]. The schematic diagram of a TIQ circuit, example transfer characteristic, and basic formulas describing the circuit operation assuming the standard square-law MOS transistor model are shown in Fig.…”

“…In this paper, a fully autonomous trimming technique is proposed for the TIQ-based comparator through body biasing in Fully Depleted Silicon-on-Insulator (FDSOI) CMOS technology [14]. The proposed technique allows tuning V GTH with a single bias voltage, eliminating the need for circuit degeneration (thus, maximizing comparator speed), the use of switches (thus, minimizing the input capacitance), and the use of bias voltages within the core supply range ( [12], and V GTH tuning techniques employing, respectively, b) resistors [10], c) transistors [9], and d) switches [8].…”

A High FoM and Low Phase Noise Edge-Injection-Based Ring Oscillator in 350 nm CMOS for Sub-GHz ADPLL Applications

“…OSI has proven to have a lower mismatch effect, enhanced performance versus temperature variations, and accurately controllable adjustable gate delay [13] in comparison to its counterparts. Besides, redundant switches were also added to trim the switching thresholds of the used CMOS logic circuits to compensate PVT variations [14]. The block diagram of proposed tunable ILRO and its transient locking signals are shown in Figure 3.…”