Tunable CMOS Delay Gate With Improved Matching Properties

Mroszczyk, Przemyslaw; Dudek, Piotr

doi:10.1109/tcsi.2014.2312491

Cited by 22 publications

(6 citation statements)

References 22 publications

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“…This mechanism determines both the pulse width at the output and, in large part, the dead time. To guarantee the stability of the monostable and to get sharp edges at the output, an inverting Schmitt trigger was added, while, to improve the linearity of the CSI controls, a current mirror was included [35]. The slew rate of the output was maximized, unlike in [34], using a custom buffering chain to the bonding pad.…”

Section: Spad Designmentioning

confidence: 99%

A Low-Noise CMOS SPAD Pixel With 12.1 Ps SPTR and 3 Ns Dead Time

Gramuglia

Bruschini

et al. 2022

IEEE J. Select. Topics Quantum Electron.

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Section: Spad Designmentioning

confidence: 99%

A Low-Noise CMOS SPAD Pixel With 12.1 Ps SPTR and 3 Ns Dead Time

Gramuglia

Bruschini

et al. 2022

IEEE J. Select. Topics Quantum Electron.

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“…The delay stage consists of a current adjustable current mirror and a seven-stage current starved inverter (CSI). The CSI stage consists of a current source and an inverter, and the maximum dynamic current of the inverter is determined by the current source [42]. The current source of each CSI stage of the delay stage is determined by the current mirror, and this current is controlled by the control voltage (VC) of the reference current source.…”

Section: Uwb Pulse Generatormentioning

confidence: 99%

An Energy-Efficient UWB Transmitter with Wireless Injection Locking for RF Energy-Harvesting Sensors

Kim

Heo

Kwon

2021

Sensors

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An ultralow-power ultrawideband (UWB) transmitter with an energy-efficient injection-locked radio frequency (RF) clock harvester that generates a carrier from an RF signal is proposed for RF energy-harvesting Internet-of-Things (IoT) sensor applications. The energy-efficient RF clock harvester based on the injection-locked ring oscillator (ILRO) is proposed to achieve optimal locking range and minimum input sensitivity to obtain an injection-locked 450 MHz clock in ultralow-power operation. A current-starved inverter-based delay stage is adopted that allows delay adjustment by bias voltage to minimize dynamic current consumption while maintaining a constant delay regardless of changes in process, supply voltage, and temperature (PVT). To minimize static current consumption, a UWB transmitter based on a digital-based UWB pulse generator and a pulse-driven switching drive amplifier is proposed. The proposed injection-locked RF clock harvester achieves the best RF input sensitivity of −34 dBm at a power consumption of 2.03 μW, enabling energy-efficient clock harvesting from low RF input power. In ultralow-power operation, a 23.8% locking range is achieved at the RF injection power of –15 dBm to cope with frequency changes due to PVT variations. The proposed UWB transmitter with RF clock harvester achieves the lowest energy consumption per pulse with an average power consumption of 97.03 μW and an energy consumption of 19.41 pJ/pulse, enabling operation with the energy available in RF energy-harvesting applications.

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“…1 b because when V in is high, C p and C L are pre‐charged to different voltages ( V dd and ground, respectively), hence shorting them through M 3 causes transient nonlinearity. Incorporating the output split inverter technique [6] in Fig. 1 c solves this problem.…”

Section: Proposed Ccdu Topologymentioning

confidence: 99%

Highly linear current‐controlled delay unit

2015

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A highly linear current-controlled delay unit (CCDU) is presented. The proposed design linearly delays an input clock edge against an applied input current. The topology features a directly proportional input/ output relation compared with an inversely proportional one in the traditional current-starved inverter (CSI). The proposed CCDU features a THD of only 0.15% compared with 22.6% in a conventional CSI over the same input dynamic current range of 180 nA. The proposed CCDU is implemented in 65 nm CMOS and consumes only 0.74 μW. An analogue-time-digital ADC is simulated using the proposed CCDU as a front-end block, achieving a resolution (ENOB) of 9.07 bits. Monte Carlo analysis confirms the linearity of the proposed CCDU under mismatch and process variation.Introduction: Low-power analogue-to-digital converters (ADCs) are widely used in wireless sensors and in biomedical fields. For certain distributed sensing applications the speed and resolution of the ADC are less important than the overall power consumption [1]. The ADC proposed in [2] utilises a current mode ring oscillator for conversion. The time mode delta-sigma ADC depicted in [3] utilises a traditional current-starved inverter to tune the oscillator frequency. Most of the time mode and oscillator-based ADCs utilise delay elements (DEs) for analogue-to-time conversion. As such, the design of DEs directly impacts on the performance of such ADCs.Traditional current-starved inverters exhibit an inversely proportional analogue-to-delay conversion relationship [3][4] that is inherently nonlinear. This Letter proposes a new current-controlled delay unit featuring a linear, directly proportional analogue-to-time transfer function. The linearity of the proposed current-controlled delay unit (CCDU) is verified by incorporating its extracted transfer function in a time mode ADC yielding an effective number of bits (ENOB) of 9.07 bits over an input dynamic range of 180 nA.

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Tunable CMOS Delay Gate With Improved Matching Properties

Cited by 22 publications

References 22 publications

A Low-Noise CMOS SPAD Pixel With 12.1 Ps SPTR and 3 Ns Dead Time

A Low-Noise CMOS SPAD Pixel With 12.1 Ps SPTR and 3 Ns Dead Time

An Energy-Efficient UWB Transmitter with Wireless Injection Locking for RF Energy-Harvesting Sensors

Highly linear current‐controlled delay unit

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