The objective of this paper is to provide a comprehensive analysis and solution for sympathetic tripping in distribution network. Al Ain Distribution Company (AADC) is responsible to operate and maintain the power distribution from 0.415 kV up to and including 33 kV level in the eastern region of Abu Dhabi emirate. AADC is always keen to provide safe and secure power supply to its customers. This paper analyses the sympathetic tripping problems and provides solution using an economical, safe, secure, and reliable scheme with utmost care, in order to minimize the damage to equipments and ensure continuity of power supply to customers as far as practicable in AADC network. The scheme is developed in combination of overcurrent, under voltage and negative sequence functions, which are readily available in numerical protection relays. The solution provided in this paper not only analyses modern relays/schemes, but also the possibility of improving existing protection scheme problems, where electromechanical relays are available with required modification without major cost impact.

This paper presents a graphical user interface (GUI) uses Particle Swarm Optimization (PSO), which is used to find the optimal locations and sizing parameters of multi type Flexible AC transmission systems (FACTS) devices in complex power systems. The GUI toolbox, offers user to choose a power system network, PSO settings and the type and number of FACTS devices for the selected network. In this paper, three different FACTS devices are implemented: SVC, TCSC and TCPST. FACTS devices are used to increase the system loadability, by reducing power flow on overloaded lines, transmission line losses, improving system stability and security. With this can make the transmission system more energy-efficient. PSO used here for optimally allocating and sizing the multiple type FACTS in a standardized power network (IEEE 30 bus system) in order to improve voltage profile, minimizing power system total losses and maximizing system loadability with respect to the size of FACTS.

A highly linear current-controlled delay unit (CCDU) is presented. The proposed design linearly delays an input clock edge against an applied input current. The topology features a directly proportional input/ output relation compared with an inversely proportional one in the traditional current-starved inverter (CSI). The proposed CCDU features a THD of only 0.15% compared with 22.6% in a conventional CSI over the same input dynamic current range of 180 nA. The proposed CCDU is implemented in 65 nm CMOS and consumes only 0.74 μW. An analogue-time-digital ADC is simulated using the proposed CCDU as a front-end block, achieving a resolution (ENOB) of 9.07 bits. Monte Carlo analysis confirms the linearity of the proposed CCDU under mismatch and process variation.Introduction: Low-power analogue-to-digital converters (ADCs) are widely used in wireless sensors and in biomedical fields. For certain distributed sensing applications the speed and resolution of the ADC are less important than the overall power consumption [1]. The ADC proposed in [2] utilises a current mode ring oscillator for conversion. The time mode delta-sigma ADC depicted in [3] utilises a traditional current-starved inverter to tune the oscillator frequency. Most of the time mode and oscillator-based ADCs utilise delay elements (DEs) for analogue-to-time conversion. As such, the design of DEs directly impacts on the performance of such ADCs.Traditional current-starved inverters exhibit an inversely proportional analogue-to-delay conversion relationship [3][4] that is inherently nonlinear. This Letter proposes a new current-controlled delay unit featuring a linear, directly proportional analogue-to-time transfer function. The linearity of the proposed current-controlled delay unit (CCDU) is verified by incorporating its extracted transfer function in a time mode ADC yielding an effective number of bits (ENOB) of 9.07 bits over an input dynamic range of 180 nA.