Highly linear current‐controlled delay unit

Abstract

A highly linear current-controlled delay unit (CCDU) is presented. The proposed design linearly delays an input clock edge against an applied input current. The topology features a directly proportional input/ output relation compared with an inversely proportional one in the traditional current-starved inverter (CSI). The proposed CCDU features a THD of only 0.15% compared with 22.6% in a conventional CSI over the same input dynamic current range of 180 nA. The proposed CCDU is implemented in 65 nm CMOS and consumes only 0.74 μW. An analogue-time-digital ADC is simulated using the proposed CCDU as a front-end block, achieving a resolution (ENOB) of 9.07 bits. Monte Carlo analysis confirms the linearity of the proposed CCDU under mismatch and process variation.Introduction: Low-power analogue-to-digital converters (ADCs) are widely used in wireless sensors and in biomedical fields. For certain distributed sensing applications the speed and resolution of the ADC are less important than the overall power consumption [1]. The ADC proposed in [2] utilises a current mode ring oscillator for conversion. The time mode delta-sigma ADC depicted in [3] utilises a traditional current-starved inverter to tune the oscillator frequency. Most of the time mode and oscillator-based ADCs utilise delay elements (DEs) for analogue-to-time conversion. As such, the design of DEs directly impacts on the performance of such ADCs.Traditional current-starved inverters exhibit an inversely proportional analogue-to-delay conversion relationship [3][4] that is inherently nonlinear. This Letter proposes a new current-controlled delay unit featuring a linear, directly proportional analogue-to-time transfer function. The linearity of the proposed current-controlled delay unit (CCDU) is verified by incorporating its extracted transfer function in a time mode ADC yielding an effective number of bits (ENOB) of 9.07 bits over an input dynamic range of 180 nA.