Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays

Mroszczyk, Przemyslaw; Dudek, Piotr

doi:10.1109/ecctd.2013.6662312

Cited by 3 publications

(2 citation statements)

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“…978-1-4799-6007-1/14/$31.00 ©2014 IEEE network is shown in Fig.1 for a 1-D array case. The rest of the evaluation, masking and input transistors are omitted for the sake of clarity and can be considered essentially the same as in [1]. Throughout this paper, NMOS pull-down transistors are pictured as simple switches.…”

Section: System and Circuit Level Structurementioning

confidence: 99%

“…The simulations were performed with Eldo using 130nm CMOS process, 0.5V power supply and using minimum size transistors in the circuit shown in Fig.2. The PEs contained also the weak pull-up and reset-inverter similarly to [1].The length of the weak pull-up transistor was higher from the minimum as well as the widths of the reset-inverter were larger than the minimum. Also, the reset voltage was kept at 0.18V after the reset.…”

Section: Simulationsmentioning

confidence: 99%

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Additional local propagation stopper circuit for asynchronous binary wave computing

Paasio

2014

2014 14th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA)

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In this abstract, we propose a new method to control the propagation stopping condition locally for asynchronous binary propagation networks. Additional switches are introduced to the Wired-OR pull-down path branches, where the switches are controlled by logic gate outputs receiving their inputs from the PE outputs in the neighborhood. An example for a 1-D case for object center pixel extraction is given with simulation results and with three neighborhood connection topologies for the new stopper circuitry. The properties of these three variants are also discussed from the end result point of view.

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Section: System and Circuit Level Structurementioning

confidence: 99%

Section: Simulationsmentioning

confidence: 99%