A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression

Abstract

This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled.

A 4×32-Channel Neural Recording System for Deep Brain Stimulation Systems

“…Recent designs of AFE have achieved very low IRN value of 1 mV rms to 3 mV rms [25,28], but this requires an undesirable amount of power and area. Furthermore, such a low IRN is unnecessary in the context of the thermal noise and biological noise experienced at typical recording bandwidths of 450 Hz to 5 kHz: the average thermal noise from an electrode and the biological noise resulting from the activity of surrounding neurons are around 6.2 mV rms and 10.2 mV rms respectively [29].…”

Advances in Microelectronics for Implantable Medical Devices

“…Numerous designs of neural amplifier based on the circuit in Figure 6 or with some variations (e.g., in the realization of the pseudoresistors, use of fully-differential topology with one or two stage OTAs, use of current-reuse techniques to double the transconductance, and so forth [35][36][37][38][39]) have been reported in the literature, including commercial amplifier chips by Intan Technologies, LLC (http://www.intantech.com/). Methods for effective optimization of a recording channel in terms of its power consumption, input-referred voltage noise, silicon area, and technology used are discussed in [40].…”

“…In addition, the system in Figure 11(b) has the advantage that is easily scalable by replicating the channels. A very compact circuit implementation for the topology in Figure 11(b) is described in [35], requiring a silicon area of only 0.054 mm 2 per channel in a 130-nm CMOS process technology.…”

Feature extraction using first and second derivative extrema (FSDE) for real-time and hardware-efficient spike sorting

“…This has allowed both electronics and electrodes to be scalable and manufacturable with sub-micron resolution features. Systems including multi-electrode arrays (MEAs) (Maynard et al, 1997) and multi-channel neural interface chips (Harrison et al, 2007;Rodriguez-Perez et al, 2012;Paraskevopoulou and Constandinou, 2012;Gao et al, 2012) can now be engineered for recording single unit activity with excellent precision, repeatability and reliability.…”